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Additive manufacturing (AM) process chain relies heavily on cloud resources and software programs. Cybersecurity has become a major concern for such resources. AM produces physical components, which can be compromised for quality by many other means and can be reverse engineered for unauthorized reproduction. This work is focused on taking advantage of layer-by-layer manufacturing process of AM to embed codes inside the components and reading them using image acquisition methods. The example of a widely used QR code format is used, but the same scheme can be used for other formats or alphanumeric strings. The code is segmented in a large number of parts for obfuscation. The results show that segmentation and embedding the code in numerous layers help in eliminating the effect of embedded features on the mechanical properties of the part. Such embedded codes can be used for parts produced by fused filament fabrication, inkjet printing, and selective laser sintering technologies for product authentication and identification of counterfeits. Post processing methods such as heat treatments and hot isostatic pressing may remove or distort these codes; therefore, analysis of AM method and threat level is required to determine if the proposed strategy can be useful for a particular product.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

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