Systematic Software-Based Self-Test for Pipelined Processors

Abstract

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

“…First of all, we have selected 6 SBST programs [8][12] [16][17] [18] from the literature for testing the Functional Units embedded in the processor: each of them has been encoded in architecture-independent pseudo-code and has been inserted in the starting library. At the end of the fragmentation step we obtained a Fragments Library composed of 520 architecture-independent Fragments, while at the end of the Customization step the Custom Fragments Library was composed of 989 Custom Fragments.…”

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

“…The resulting test programs were loop-based pieces of code that deterministically provide the modules under testing with a series of data inputs carefully selected. The methods were based on analysis of data dependencies of available SBST programs and general parameters of the pipeline architecture and memory system with remarkable results -95 % stuck-at fault coverage for two RISC processors with pipelined architectures: MiniMIPS and OpenRISC 1200 [14].…”

Instruction based Built-in-Testing of Instruction Select Multiplexer in Arithmetic Logic Unit

“…The testing of microprocessors' functionality is an active research area and has been intensively studied by researchers for pipelined microprocessors [2] and even for multiprocessors [3]. Despite the significant advantages of functionality test based on data paths, structural test of microprocessor [4] that concentrates on operation of control logic is highly required.…”