BackgroundCell-derived microvesicles (MVs) have been described as a new mechanism of cell-to-cell communication. MVs after internalization within target cells may deliver genetic information. Human bone marrow derived mesenchymal stem cells (MSCs) and liver resident stem cells (HLSCs) were shown to release MVs shuttling functional mRNAs. The aim of the present study was to evaluate whether MVs derived from MSCs and HLSCs contained selected micro-RNAs (miRNAs).Methodology/Principal FindingsMVs were isolated from MSCs and HLSCs. The presence in MVs of selected ribonucleoproteins involved in the traffic and stabilization of RNA was evaluated. We observed that MVs contained TIA, TIAR and HuR multifunctional proteins expressed in nuclei and stress granules, Stau1 and 2 implicated in the transport and stability of mRNA and Ago2 involved in miRNA transport and processing. RNA extracted from MVs and cells of origin was profiled for 365 known human mature miRNAs by real time PCR. Hierarchical clustering and similarity analysis of miRNAs showed 41 co-expressed miRNAs in MVs and cells. Some miRNAs were accumulated within MVs and absent in the cells after MV release; others were retained within the cells and not secreted in MVs. Gene ontology analysis of predicted and validated targets showed that the high expressed miRNAs in cells and MVs could be involved in multi-organ development, cell survival and differentiation. Few selected miRNAs shuttled by MVs were also associated with the immune system regulation. The highly expressed miRNAs in MVs were transferred to target cells after MV incorporation.ConclusionsThis study demonstrated that MVs contained ribonucleoproteins involved in the intracellular traffic of RNA and selected pattern of miRNAs, suggesting a dynamic regulation of RNA compartmentalization in MVs. The observation that MV-highly expressed miRNAs were transferred to target cells, rises the possibility that the biological effect of stem cells may, at least in part, depend on MV-shuttled miRNAs. Data generated from this study, stimulate further functional investigations on the predicted target genes and pathways involved in the biological effect of human adult stem cells.

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Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.

Abstract-We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RAL-ISIS facility. The ISIS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 10 7 and 10 8 in the energy range 10-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications.

The growing adoption of SRAM-based Field Programmable Gate Arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single Event Upsets (SEUs) affecting the configuration memory of SRAM-based FPGAs are a major concern, since they can permanently affect the function implemented by the device. We exploited a fault-injection environment developed at our institution to analyze the impact of such faults on SRAMbased FPGAs when fault tolerant design techniques are adopted. The experimental results allow quantitative evaluations of the effects of these faults, and show that the sensitivity of the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.