On the evaluation of SEU sensitiveness in SRAM-based FPGAs

Abstract

The growing adoption of SRAM-based Field Programmable Gate Arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single Event Upsets (SEUs) affecting the configuration memory of SRAM-based FPGAs are a major concern, since they can permanently affect the function implemented by the device. We exploited a fault-injection environment developed at our institution to analyze the impact of such faults on SRAMbased FPGAs when fault tolerant design techniques are adopted. The experimental results allow quantitative evaluations of the effects of these faults, and show that the sensitivity of the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

“…Additionally, radiation can cause permanent damage to silicon devices over time, rendering all or part of the device unusable. Authors of [21] have concluded that the TMR technique is not able to mask all the faults induced by SEUs. TMR is often coupled with scrubbing [8] to avoid fault accumulation.…”

SEU-aware resource binding for modular redundancy based designs on FPGAs

“…SRAM-based FPGA devices are becoming more sensitive to soft errors due to shrinking feature size, high density, and lower operating voltages [1][2][3][4]. Functionality and connectivity of implemented circuits on SRAM-based FPGAs can be damaged if a SEU caused by soft errors flips a configuration bit.…”

“…Functionality and connectivity of implemented circuits on SRAM-based FPGAs can be damaged if a SEU caused by soft errors flips a configuration bit. SRAM-based FPGAs are rather more vulnerable to SEUs than their ASIC counterparts [1][2][3][4]. This paper focuses on SEU mitigation in high level synthesis for SRAM-based FPGAs.…”

“…The capability of TMR for FPGA designs in tolerating SEUs has been studied in [2][3][4]. It has been observed that TMR schemes are able to only partially mitigate the effects of SEUs in routing configuration bits, which comprises around 90% of all configuration bits.…”

A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs

“…In [9], [10], a software/hardware fault injection platform is presented that allows direct manipulation of the configuration bitstream on Xilinx's Spartan2 FPGA devices. An Enhanced Parallel Port (EPP) interface is employed to connect to the fault emulator which is embedded in the target FPGA device.…”