Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs

Tsormpatzoglou, A.; Dimitriadis, C. A.; Clerc, R.; Pananakakis, G.; Ghibaudo, G.

doi:10.1109/ted.2008.927394

Cited by 86 publications

(42 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The calculated result shows a good agreement with References [16,17] model results for LX150 nm. However, an appreciable difference is observed between Equation (14) and Reference [16] results for deep submicron SDG MOS devices. The main reason for this difference is the dependence of Q th on channel length as mentioned in Reference [16] whereas in the proposed model (14), Q th is assumed as a constant.…”

Section: Proposed Analytical Models and Discussionsupporting

confidence: 86%

“…At threshold, V gs 5 V th and Q inv. 5 Q th ; therefore, threshold voltage is given as; Figure 6 compares the threshold voltage V th obtained from the developed model (14) with References [16,17] model results as a function of channel length. The calculated result shows a good agreement with References [16,17] model results for LX150 nm.…”

Section: Proposed Analytical Models and Discussionmentioning

confidence: 99%

“…5 Q th ; therefore, threshold voltage is given as; Figure 6 compares the threshold voltage V th obtained from the developed model (14) with References [16,17] model results as a function of channel length. The calculated result shows a good agreement with References [16,17] model results for LX150 nm. However, an appreciable difference is observed between Equation (14) and Reference [16] results for deep submicron SDG MOS devices.…”

Section: Proposed Analytical Models and Discussionmentioning

confidence: 99%

See 2 more Smart Citations

An analytical study of undoped symmetric double gate MOSFET (SDG)

Singh

2010

Int J Numerical Modelling

View full text Add to dashboard Cite

SUMMARYIn the present paper, compact analytical models for the threshold voltage, threshold voltage roll-off and subthreshold swing of undoped symmetrical double-gate MOSFET have been developed based on analytical solution of two-dimensional Poisson's equation for potential distribution. The developed models include drain-induced barrier lowering (DIBL) through the V ds -dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling.

show abstract

Section: Proposed Analytical Models and Discussionsupporting

confidence: 86%

Section: Proposed Analytical Models and Discussionmentioning

confidence: 99%

Section: Proposed Analytical Models and Discussionmentioning

confidence: 99%

See 1 more Smart Citation

An analytical study of undoped symmetric double gate MOSFET (SDG)

Singh

2010

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…However, as (6) and (8) show, the gain from increasing t ox quickly diminishes as t ox increases. In undoped devices, the gate quickly loses control over the channel if t ox is increased aggressively [20]. In fact, the overall leakage first decreases as t ox is increased.…”

Section: A Design Of High-v Th Devicesmentioning

confidence: 99%

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Rostami

Mohanram

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-V th independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.

show abstract

“…Beyond a certain oxide thickness, however, this trend reverses and standby leakage current increases due to severe DIBL effects. In these undoped devices, the gate loses control over the channel if the oxide thickness is increased aggressively [13]. So, there exists an optimum gate oxide thickness for obtaining minimum leakage.…”

Section: Dual-v Th Independent-gate Finfetsmentioning

confidence: 99%

Novel dual-V<inf>th</inf> independent-gate FinFET circuits

Rostami¹,

Mohanram²

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

View full text Add to dashboard Cite

This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-V th independent-gate FinFETs. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.

show abstract

Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs

Cited by 86 publications

References 11 publications

An analytical study of undoped symmetric double gate MOSFET (SDG)

An analytical study of undoped symmetric double gate MOSFET (SDG)

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Novel dual-V<inf>th</inf> independent-gate FinFET circuits

Contact Info

Product

Resources

About