Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

Abstract

Conventional integrated circuits comprise a single layer of transistors interconnected with multiple layers of metal wiring. The density, speed, and power dissipation of these two-dimensional devices are increasingly limited by the wiring [1], providing strong motivation to take advantage of the third dimension. Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked allow shorter interconnect paths and hence are expected to lead to improved logic devices, memories, CPUs, and photo sensors [2]. These circuits require high-density vertical interconnections (3D vias) comparable in aspect ratio to present multilevel metal vias [3]. Fabrication and characterization of 3D ring oscillators and backilluminated 64x64 active pixel sensor arrays with fully parallel A/D conversion are described here that use a 3D integration technology that utilizes silicon-on-insulator (SOI) wafers to achieve stacking of multiple circuit layers and unrestricted placement of dense 3D vias.Each pixel of the imager is composed of a photodiode on one wafer and an analog-to-digital (A/D) converter on the other wafer. The oscillators consist of inverters alternating between wafers. That is, a CMOS inverter in one wafer is connected to the next inverter in the other wafer. The construction of these circuits consists of bonding and interconnecting a SOI wafer with imaging circuits and inverters to a SOI wafer with A/D converter circuits and inverters. The imager circuits are fabricated in a 10µm epitaxial silicon layer on a 0.3µm bonded and etched back SOI layer with a 1µm buried oxide (BOX). The epi thickness was chosen for good optical performance in the visible and nearinfrared spectrum. The A/D circuits were fabricated in a 1µm SOI layer with a 1µm BOX. Both wafers are processed with the same two-level metal 0.8µm CMOS process designed to operate at 5 V. Prior to CMOS fabrication, silicon trenches are etched through the SOI layer of the A/D wafer and filled with deposited oxide to form channels through which 3D vias will be etched to interconnect the two active layers.After wafer fabrication and test, the A/D wafer is inverted, aligned to the imager wafer using an infrared aligner, and bonded with a 3µm thick adhesive. The bulk silicon is then etched from the A/D wafer to expose the BOX. The BOX is used as a stop for the silicon etch to produce a thin, uniform active layer and is an essential step in the 3D assembly technology. A set of shallow 3D vias is etched through the BOX, trench, and deposited oxides of the A/D wafer to expose the bottom side of metal pads on the first metal layer of the A/D wafer. A deep set of 3D vias is defined and etched entirely through the A/D wafer plus the adhesive to expose metal pads on the second metal layer of the imager wafer. The 3D vias are 6µm square and are nominally 2.7 and 7.5µm deep for the shallow and deep vias, respectively. An aluminum alloy is deposited on the BOX by bias sputtering and patterned to connect the metal pads of the two wafers. The...

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