Abstract:Abstract-The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch t… Show more
“…If 3D integration technology is introduced in the future to stack several mrFPGAs together, at least two more times of improvements in density and speedup, i.e. 10x and 4.5x respectively, are both expected, according to the experimental results on 3D architecture in [17].…”
Section: B Evaluation Resultsmentioning
confidence: 98%
“…A 3D FPGA architecture was proposed in [17]. It partitions the transistors in the routing structure and logic structure of conventional FPGA into multiple active layers and stacks the layers via monolithic stacking, a 3D integration technology the author proposes to use as shown in Fig.…”
Section: B Recent Work On Fpgas Using Emerging Technologiesmentioning
confidence: 99%
“…In [14] and [18] two FPGA architectures are proposed using emerging NVMs and through-silicon-via (TSV) based 3D integration. Similar to the monolithic stacking in [17], they also move all the transistors in the routing structure of FPGA to the top die over the logic structure die with TSV connections between them as shown in Fig. 2b.…”
Section: B Recent Work On Fpgas Using Emerging Technologiesmentioning
Abstract-In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D diestacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.
“…If 3D integration technology is introduced in the future to stack several mrFPGAs together, at least two more times of improvements in density and speedup, i.e. 10x and 4.5x respectively, are both expected, according to the experimental results on 3D architecture in [17].…”
Section: B Evaluation Resultsmentioning
confidence: 98%
“…A 3D FPGA architecture was proposed in [17]. It partitions the transistors in the routing structure and logic structure of conventional FPGA into multiple active layers and stacks the layers via monolithic stacking, a 3D integration technology the author proposes to use as shown in Fig.…”
Section: B Recent Work On Fpgas Using Emerging Technologiesmentioning
confidence: 99%
“…In [14] and [18] two FPGA architectures are proposed using emerging NVMs and through-silicon-via (TSV) based 3D integration. Similar to the monolithic stacking in [17], they also move all the transistors in the routing structure of FPGA to the top die over the logic structure die with TSV connections between them as shown in Fig. 2b.…”
Section: B Recent Work On Fpgas Using Emerging Technologiesmentioning
Abstract-In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D diestacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.
“…This approach requires monolithic 3D integration because of the high density of inter-layer via required. The study in [6] has shown that such stacking cans achieve3.2 times higher logic density, 1.7 times lower delay, and 1.7 times lower dynamic power consumption than a baseline2D-FPGA implemented in 65nm CMOS technology. These improvements are achieved with appropriate optimization of buffer and transistor sizes, but without any change to the FPGA architecture.…”
Section: C) Programming Overhead Stackingmentioning
“…Renewed interest in 3D device packaging has direct applicability to FPGA logic [140] and routing structures [139]. As transistor channel widths shrink deep into the submicron realm, the manufacturability of reliable FPGA routing becomes an issue.…”
Section: Challenges In Basic Routing Architecturementioning
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.