During development, the embryonic telencephalon is patterned into different areas that give rise to distinct adult brain structures. Several secreted signaling molecules are expressed at putative signaling centers in the early telencephalon. In particular, Fgf8 is expressed at the anterior end of the telencephalon and is hypothesized to pattern it along the anteroposterior (AP) axis. Using a CRE/loxP genetic approach to disrupt genes in the telencephalon, we address the role of FGF signaling directly in vivo by abolishing expression of the FGF receptor Fgfr1. In the Fgfr1-deficient telencephalon, AP patterning is largely normal. However, morphological defects are observed at the anterior end of the telencephalon. Most notably, the olfactory bulbs do not form normally. Examination of the proliferation state of anterior telencephalic cells supports a model for olfactory bulb formation in which an FGF-dependent decrease in proliferation is required for initial bulb evagination. Together the results demonstrate an essential role for Fgfr1 in patterning and morphogenesis of the telencephalon.

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Abstract-The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are ≤ 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node.

Abstract-The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are ≤ 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node.

No abstract