Performance benefits of monolithically stacked 3D-FPGA

Lin, Mingjie; Gamal, Abbas El; Lu, Yi-Chang; Wong, S.S.

doi:10.1145/1117201.1117219

Cited by 76 publications

(64 citation statements)

References 23 publications

(20 reference statements)

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“…Lin et al [8] introduced a monolithically stacked 3D FPGA with separate layers for logic, routing, and configuration bits; unlike our work, their proposal was not a multi-context FPGA.…”

Section: Related Workmentioning

confidence: 89%

“…3. We can calculate the area of the tile width in comparison to pitch and copper bond size: pitch_width = bond_width + spacing_width (8) tile_width = 3 × bond_width + 2 × spacing_width (9) tile_height = 3 × bond_width + 2 × spacing_width (10) A tile = tile_width × tile_height (11) We make the following simplifying assumptions: bond_width = bond_height (12) spacing_width = spacing_height (13) num_horizontal_bonds = num_vertical_bonds (14) From these assumptions, we can replace Eq. (11) with (15) …”

Section: Morrow Et Al's [12]mentioning

confidence: 99%

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Using 3D integration technology to realize multi-context FPGAs

Cevrero¹,

Athanasopoulos²,

Parandeh-Afshar

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

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This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). The latency between reconfigurations, 8.42μs, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.

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“…Lin et al [8] introduced a monolithically stacked 3D FPGA with separate layers for logic, routing, and configuration bits; unlike our work, their proposal was not a multi-context FPGA.…”

Section: Related Workmentioning

confidence: 89%

Section: Morrow Et Al's [12]mentioning

confidence: 99%

Using 3D integration technology to realize multi-context FPGAs

Cevrero¹,

Athanasopoulos²,

Parandeh-Afshar

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

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show abstract

“…Part of the parameters are from [4] and [30]. Fig.14(a) shows the package model assuming a face-toback stacking.…”

Section: System Configurationmentioning

confidence: 99%

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Wang

Liu

Yang

et al. 2013

J. Comput. Sci. Technol.

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Abstract3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.

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“…3DMI technology promises very small 3D contacts in the order of a few 100nm [Jung et al 2007], thereby enabling circuit partitioning at a fine granularity. Few publications proposed 3D FPGA architecture employing 3DMI technology Lin et al 2007]. The authors proposed to partition the blocks with the SRAM cells (used for configuration) in one layer and the logic part on the other layer.…”

Section: Previous Work In 3d Monolithic Integrated Circuitsmentioning

confidence: 99%

Cell transformations and physical design techniques for 3D monolithic integrated circuits

Bobba

Chakraborty

Thomas

et al. 2013

J. Emerg. Technol. Comput. Syst.

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3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique, cell-on-cell stacking, and a physical design technique (CELONCEL PD ) aimed at placing cells transformed with cell-on-cell stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.

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Performance benefits of monolithically stacked 3D-FPGA

Cited by 76 publications

References 23 publications

Using 3D integration technology to realize multi-context FPGAs

Using 3D integration technology to realize multi-context FPGAs

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Cell transformations and physical design techniques for 3D monolithic integrated circuits

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