Abstract-

We have designed and fabricated double-gate ambipolar field-effect transistors, which exhibit p-type and n-type characteristics by controlling the polarity of the second gate. In this work, we present an approach for designing an efficient regular layout, called Sea-of-Tiles (SoTs). First, we address gate-level routing congestion by proposing compact layout techniques and novel symbolic-layout styles. Second, we design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks on the SoT. Our study shows that SoT with Tile G2 and TileG 1h2 , on an average, outperforms the one with Tile G1 and Tile G3 by 16% and 10% in area utilization, respectively.

Abstract-The invention of the memristor enables new possibilities for computation and non-volatile memory storage. In this paper we propose a Generic Memristive Structure (GMS) for 3-D FPGA applications. The GMS cell is demonstrated to be utilized for steering logic useful for multiplexing signals, thus replacing the traditional pass-gates in FPGAs. Moreover, the same GMS cell can be utilized for programmable memories as a replacement for the SRAMs employed in the look-up tables of FPGAs. A fabricated GMS cell is presented and its use in FPGA architecture is demonstrated by the area and delay improvement for several architectural benchmarks.

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI enables manufacturing multiple active layers very close to each other. In this work we propose two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacking). A placement tool (CELONCEL-placer) targeting the Cell-on-Cell placement problem is

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/design co-optimization approach for designing logic tiles for double-gate silicon nanowire field effect transistors (DG-SiNWFET) technology. A compact Verilog-A model of the device is extracted from TCAD simulations. Cell libraries with different tile configurations are mapped to study the performance of DG-SiNWFET technology at various technology nodes. With an optimal tile size comprising of 6 vertically-stacked nanowires, we observe 1.6x improvement in area, 2x decrease in the leakage power and 1.8x improvement in delay when compared to Si-CMOS.I.

-The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logic-to-GDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFETbased inverter can achieve gains, with respect to the EnergyDelay Product (EDP) metric, of more than 4x in delay, 2x in energy/cycle and significant area savings (more than 30%) when compared to a corresponding CMOS inverter benchmarked with an industrial 65nm technology.

No abstract

3-D monolithic integration (3DMI),