CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Bobba, Shashikanth; Chakraborty, Anirban; Thomas, Olivier; Batude, P.; Ernst, T.; Faynot, O.; Pan, David Z.; Micheli, Giovanni De

doi:10.1109/aspdac.2011.5722210

Cited by 45 publications

(25 citation statements)

References 15 publications

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“…Various design methodologies for M3D digital circuits have been proposed so far, [5], [6]. To the best of our knowledge there is no prior work on M3D integration for RF/AMS ICs.…”

Section: Related Workmentioning

confidence: 99%

Enabling area efficient RF ICs through monolithic 3D integration

Chaourani

Hellstrcom

Rodriguez

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

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“…Various design methodologies for M3D digital circuits have been proposed so far, [5], [6]. To the best of our knowledge there is no prior work on M3D integration for RF/AMS ICs.…”

Section: Related Workmentioning

confidence: 99%

Enabling area efficient RF ICs through monolithic 3D integration

Chaourani

Hellstrcom

Rodriguez

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

View full text Add to dashboard Cite

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“…In fact, multi- tier (more than two tiers) 3D ICs are expected to provide more benefits than two-tier 3D ICs [5] and some monolithic 3D integration technologies can fabricate multiple device layers [6]. In this paper, therefore, we also design multi-tier monolithic 3D ICs using the uniform-scaling-based and our placement algorithms and compare the quality of the algorithms.…”

Section: Introductionmentioning

confidence: 97%

Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs

Lin

Pande

Kim

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniformscaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

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“…1) largely reduce the physical dimensions of the vertical connections to be of only metal-via sizes. The high-density integration makes monolithic 3D-IC a promising solution [5], [6] to cope with interconnect-limited 2D-ICs, where most of the problems are essentially caused by the high interconnect density at gate level.…”

Section: Introductionmentioning

confidence: 99%

Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs

Zhuang

Samadi

et al. 2013

2013 International Conference on Communications, Circuits and Systems (ICCCAS)

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Abstract-Recent advances in three-dimensional integrated circuits (3D-ICs) offer a new dimension of design exploration at traditional physical architecture of datapath components. The emerging monolithic inter-tier vias (MIVs) provides more advantages over through-silicon vias (TSVs) in terms of higher integration density and lower design overhead. In this work, we develop a performance-driven framework which uses simulated annealing to produce gate-level 3D placement layout for rotation shifter and right arithmetic shifter design. Compared to the optimum 2D layout, the critical path of our solution is much shorter with limited overhead on total wirelength. Our work indicates that by gatelevel 3D-IC integration, the new physical dimension can be well leveraged with improvement on both performance and power of shifter design.

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CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Cited by 45 publications

References 15 publications

Enabling area efficient RF ICs through monolithic 3D integration

Enabling area efficient RF ICs through monolithic 3D integration

Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs

Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs

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