Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors

Bobba, Shashikanth; Marchi, Michele De; Leblebici, Yusuf; Micheli, Giovanni De

doi:10.1145/2228360.2228369

Cited by 29 publications

(33 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among these technologies, SiNWs have a CMOS compatible fabrication process that can be easily integrated by the semiconductor industry [15]. In addition, DIG ambipolar SiNWFETs enable efficient regular layout opportunities as described in [16]. The Control Gate (CG) acts as in standard unipolar FET, while the Polarity Gates (PG), connected together, control the device polarity and tune the Schottky barriers at the source/drain junctions as shown in Fig.…”

Section: Ambipolar Sinwfet Ambipolar Transistors Are Double Indepmentioning

confidence: 99%

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Turkyilmaz

Clermidy

Amarù

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

Self Cite

View full text Add to dashboard Cite

Abstract-For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self-checking ripple-carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.

show abstract

Section: Ambipolar Sinwfet Ambipolar Transistors Are Double Indepmentioning

confidence: 99%

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Turkyilmaz

Clermidy

Amarù

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

Self Cite

View full text Add to dashboard Cite

show abstract

“…With DG-SiNWFETs, the process complexity related to chemical doping is avoided thanks to the electrical device configurability. In addition, DG-SiNWFETs enable a high Ion/Ioff ratio [3] and also efficient regular layout opportunities [6].…”

Section: Double-gate Controllable Polarity Sinwfetsmentioning

confidence: 99%

“…In the proposed study, gate-level interconnects are not considered during simulations. Note that the inherent increase of wiring complexity with DG-SiNWFETs can be handled by physical design [6]. The area of the 4-transistor DG-SiNWFET configuration is 0.45 µm 2 and its worst case delay, under a load of 0.5 f F, is 15.02 ps.…”

Section: Characterization and Validationmentioning

confidence: 99%

Efficient arithmetic logic gates using double-gate silicon nanowire FETs

Amarù

Gaillardon

Micheli

2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

Self Cite

View full text Add to dashboard Cite

Abstract-Silicon NanoWire (SiNW) based Field Effect Transistors (FETs) are promising candidates to extend Moore's law in the coming years. Recently, Double-Gate (DG) SiNWFETs have been demonstrated to allow on-line configurability of n-type and p-type device polarity through the second gate. Such feature enables novel compact realizations for XOR-and MAJ-based logic gates that are intensively used in arithmetic applications. In this paper, we present a complete design framework of DGSiNWFETs technology for arithmetic logic. We characterize and validate compact arithmetic logic gates (XOR, MAJ, FA) using circuit level simulations. SiNW-based controllable polarity transistors at 22-nm technology node, first characterized at the physical level with Synopsys Sentaurus, enable a full-adder implementation about 3.8x faster than its CMOS FinFET 22-nm counterpart, according to HSPICE circuit simulations. Then, we study the application of these arithmetic gates in the automated synthesis of datapath circuits which are dominated by arithmetic operations. Experimental results show that datapath circuits synthesized in DG-SiNWFETs 22-nm technology are about 1.5x faster than in CMOS FinFET 22-nm technology while having practically the same area occupation.

show abstract

“…This terminal, mostly called Polarity Gate (PG), has to be considered from a physical design perspective since it may affect the routing complexity of the gates and of the design in general. To mitigate this effect, regular organization of devices, referred to hereafter as tiles, reduce the number of terminal to route by sharing them at the active layer [4]. Tiles are subsequently configured by routing logic signals and power lines to their different terminals.…”

Section: Introduction the Performance And Power Consumption Limitsmentioning

confidence: 99%

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements

Zografos

Gaillardon

Micheli

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

Abstract-Polarity-controllable transistors have emerged in the last few years as an adequate successor of current CMOS FinFETs. Due to the additional polarity terminal, novel physical design techniques are required. We present a novel grid-based power routing scheme able to mitigate the polarity terminal impact. The logic cells are organized in regular arrangements and easily configured using the novel power routing scheme. The impact of the placement and routing techniques used is gauged in terms of routing metal distribution, speed and area performance. Benchmark circuits are synthesized, placed and routed using commercial tools and performances are extracted. Post place and route results show 28% faster circuits compared to 22nm FinFET regular layout-based designs.

show abstract

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors

Cited by 29 publications

References 9 publications

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Efficient arithmetic logic gates using double-gate silicon nanowire FETs

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements

Contact Info

Product

Resources

About