3D VLSI with a CoolCube TM integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm². This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube TM technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.
I-INTRODUCTION: 3D-VLSI sequential processing of stacked devices offers a 3D contact pitch equal to planar contacted gate pitch. Moreover, thanks to the lithography alignment precision depending only on the stacked technology node, the via density reaches 10 8 vias/mm 2 with a 90nm-CPP technology. This 3D contact pitch allows fully leveraging the 3 rd dimension with negligible area penalty due to 3D via or landing pad size compared to packaging solutions as shown in Fig.1 [1] .3DVLSI motivations-Actually, scaling below the 28 nm technology node does not yield substantial cost reductions [2] . Among scaling challenges, the increasing interconnect delay overshadows benefits stemming from costly transistor scaling. 3D VLSI interest has been demonstrated via a Power-Performance-Area benchmark for FPGA applications stacking two layers of 14nm FDSOI technology with W/SiO2 interconnect in between [3] . Dramatic area and Energy Delay Product (EDP) reduction is achieved, with benefits exceeding those of downscaling to the 10 nm node (Figs.2&3). 3DVLSI partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. In parallel, partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [6,7] ) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III-V nFETs above SiGe pFETs [8,9] . These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI partitioning at the transistor level allows performance gain as it facilitates the cointegration of high performance n&p-FETs compared to a coplanar scheme. Finally, 3DVLSI, with its high contact density, is also anticipated as a powerful solution for heterogeneous cointegrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [10, 11] or highly miniaturized imagers [12] . Fig.4 summarizes the three main integration schemes foreseen for ...
Abstract-For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self-checking ripple-carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.
Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.
Normally off, instantly on" applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power gating techniques due to their long context restoring phase. In this paper, we propose to integrate non-volatile resistive memories in configuration cells in order to instantly restore the FPGA context. We then show that if the circuit is in 'ON' state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, for a typical application with only 1% of time spent in 'ON' state, the energy gain reaches 50%.
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