RRAM-based FPGA for "normally off, instantly on" applications

Turkyilmaz, Ogun; Onkaraiah, Santhosh; Reyboz, Marina; Clermidy, Fabien; Hraziia,; Anghel, Costin; Portal, Jean‐Michel; Bocquet, Marc

doi:10.1145/2765491.2765510

Cited by 44 publications

(11 citation statements)

References 26 publications

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“…In the proposed architecture, the logic elements exploit Non-Volatile (NV) LUTs. As other NV FPGAs, our structure does not need to be re-programmed during each power on and can benefit instant-on and normally-off properties [6]. Typically, a LUT consists of a bank of SRAMs and a multiplexer.…”

Section: B Rram-based Fpgas: Our Visionmentioning

confidence: 99%

“…Overwhelming Static Random Access Memories (SRAMs) intrinsically, RRAMs hold storage when powered down and consume zero leakage power in sleep mode. Using RRAMs as standalone memories, FPGAs can benefit a ~50% power reduction from instant power-on and normal power-off, compared to SRAM-based counterparts [6]. Furthermore, RRAMs motivate the exploration of novel FPGA architectures whose routing structures are directly employing RRAMs in the data path.…”

Section: Introduction Static Random Access Memory (Sram)-based Fieldmentioning

confidence: 99%

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A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Gaillardon

Tang

Sandrini

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable highperformance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs as well as the improved tolerance to power supply reduction, RRAM-based routing multiplexers can be used to significantly reduce the power consumption of FPGA systems with no performance compromises. By evaluating the opportunities of ultra-low-power RRAM-based FPGAs at the system level, we see an improvement of 12%, 26% and 81% in area, delay and power consumption at a mature technology node.

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Section: B Rram-based Fpgas: Our Visionmentioning

confidence: 99%

Section: Introduction Static Random Access Memory (Sram)-based Fieldmentioning

confidence: 99%

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Gaillardon

Tang

Sandrini

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…On the other hand SRAM's are un-predictable, in this way non-stability capacity is required for shutdown operations [1], [2]. Generally SRAM's are preferred than DRAM's because of it's data retaining capability.…”

Section: Introductionmentioning

confidence: 99%

Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation

Mounica¹,

Ganesh²

2016

IJECE

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Now-a-days, Energy consumption is the major key factor in Memories. By switching the circuit in off mode and with an lower voltages, leads to decrease in an power dissipation of the circuit. Compared to DRAM SRAM'S are mostly used because of their data retaining capability. The major advantage of using SRAM's rather than DRAM'S is that, they are providing fast power-on/off speeds. Hence SRAM's are more preferred over DRAM's for better instant-on operation. Generally SRAM's are classified in to two types namely volatile and non-volatile SRAM's. A non-volatile SRAM enables chip to achieve performance factors and also provides an restore operation which will be enabled by an restore signal to restore the data and also power-up operation is performed. This paper describes about novel NVSRAM circuit which produces better "instant-on operation" compared to previous techniques used in SRAM's. In addition to normal 6T SRAM core, we are using RRAM circuitry (Resistive RAM) to provide better instant-on operation. By comparing the performance factors with 8T2R and 9T2R, 8T1R design performs the best in the Nano meter scale. Thus this paper provides better performances in power, energy, propagation delay and area factors as compared with other designs. Keyword:Energy . Generally SRAM's are preferred than DRAM's because of it's data retaining capability. SRAM performs both volatile and non-volatile operations. In our project we concentrate more on non-volatile SRAM which produces instant on operation [3] . These are designed in two technologies namely transistor technology and resistive technology. In accordingly, resistive technology uses 1R and 2R series. Compared to 2R series 1R produces more non-volatile operation effectively. Hence in this project we are using resistive technology which was often called as Resistive RAM (RRAM). For controlling or flowing of current/voltage through the resistor, we are using one additional transistor which was so called as control transistor. As we know that the transistor will act as a resistor in linear region. The RRAM circuitry which we are using in this paper was act as a "Mermistor" (memory resistor) [4].As the years progressed, expanded thickness 64kb & quicker get to have been accounted for NVSVRAM'S for military applications. The programming technology of an FPGA's are generally utilizes SRAM technology [1]. The energy consumption [5] has become a major source due to an considerably increase in an leakage current while we are reducing it's supply voltage and feature size of an SRAM. Instant

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“…One of the emerging technology-driven paradigms in memory systems is represented by non-volatile (resistive) RAMs [5,6]. [7] has presented a novel design of a non-volatile SRAM (NVSRAM) memory cell that can be used for "Instant-on" operation, i.e.…”

Section: Introductionmentioning

confidence: 99%

“…The implications of adding a resistive RAM to a SRAM core are analyzed with respect to the charge at the storage node (that is also the node of critical charge in a 6T core). In the NVSRAM cells [5][6][7], the presence of at least a RRAM degrades the storage node charge compared with a 6T SRAM core. Hence, three lowpower hardened NVSRAM cell designs are proposed.…”

Section: Introductionmentioning

confidence: 99%

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance

Wei

Lombardi

Namba

2014

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A SER analysis of these cells is also pursued. An extensive evaluation and comparison of different schemes are presented.

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RRAM-based FPGA for "normally off, instantly on" applications

Cited by 44 publications

References 26 publications

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance

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