Cell transformations and physical design techniques for 3D monolithic integrated circuits

Abstract

3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique, cell-on-cell stacking, and a physical design technique (CELONCEL PD ) aimed at placing cells transformed with cell-on-cell stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

“…When designing a multi-tier M3D core, we can focus on reducing the interconnect lengths in critical paths of the design and increase the overall clock speed. However, like many other works [14][15][16][17][18][19][20][21], if we do not consider the process variation effects, the critical path could face unexpected slowdowns and the achievable frequency of the system could be affected. Therefore, in this work, we consider three different core architectures under different design scenarios as demonstrated in Reference [25].…”

“…Existing works have explored the advantages of M3D-based circuits and systems [14,15]. M3Dbased designs show significant reduction in chip area, total wirelengths, and improved energy efficiency compared to their planar counterparts [16,18].…”

Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration

“…The merits of M3D-based designs have been explored in several works [14], [15]. M3D circuits provide reduced power, performance, and area compared to their 2D counterparts.…”

“…M3D circuits provide reduced power, performance, and area compared to their 2D counterparts. Motivated by the promise of monolithic integration, the CELONCEL design framework was proposed to explore the advantage of transistor/gate-level partitioning and cell-on-cell stacking design for M3D integration [15]. It was found that the footprint and wirelength of M3D-based designs are reduced by 37.5% and 16.2% respectively over their planar counterparts at the 45 nm technology node.…”