mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Abstract

Abstract-In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D diestacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.

Design and FPGA-based implementation of a high performance 32-bit DSP processor

“…When FSM is not handing hazard, R3 <-7 and R5 <-17 (adding previous value of R3 (8) and R4 (9)) since R3 needs one more cycle to update with the most recent value of addition (7) of R1 and R2 due to two stage of pipelining. This hazard is avoided by the FSM of proposed processor which updated R5 with the result of addition (16) of most recent value of R3 (7) and R4 (9). Table III is used here to illustrate the comparison.…”

“…A design implemented on XILINX Spartan-3E has the ability to provide high throughput and avoid the lengthy development cycles, and the inherent inflexibility of conventional ASICs. In addition to this, digital filter implementation on FPGAs allow higher sampling rates than available from traditional DSP chips and lower cost [8].FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs [9]. This can help the designer to perform the basic processes faster.…”

GMS: Generic memristive structure for non-volatile FPGAs

“…In [9], a cross point for switchboxes, using the RRAMs as non-volatile switches, is proposed to route signals through low-resistive paths, or to isolate them by means of highresistive paths. The concept of routing elements based on ReRAM switches was then exploited in [10,11] for timing optimization in FPGAs.…”

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

“…The rSRAM extends the 6T SRAM with additional four memristors (M1 to M4) bridging internally and four extra transistors (MN3/MN5/ MN6/MN8) to program these memristors. The memristor, known as the resistive random-access memory (RRAM), is a two-terminal device which can be fabricated between the top metal layer and other metal layers upon transistor layer within the same die [9]. By applying specific current pulse, the memristor could switch between high resistance state (HRS) and low resistance state (LRS).…”