A single phase modulation for pulse-based inductive-coupling connection in 3D stacked chip

Abstract

This paper proposes an efficient modulation in high-speed interchip data communication with inductive-coupling wireless connection for 3D-stacked system in package (SiP). In this modulation, signal is generated only in one polarity of the digital signal transmission. Compared with BPM and NRZ modulation, it has a 50% power reduction and better crosstalk immunity.

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

“…One alternative encoding scheme is Single-Phase Modulation (SPM), proposed by [19], shown in Fig. 2(b).…”

“…As can be observed from the table, the additional SET control logic does not add significant overhead to the footprint of the transceiver, in fact only contributing between 0.1% (in the case of 28nm technology) and 14% (in the case of the 0.35 µm technology). [18], SINGLE PHASE MODULATION (SPM) [19], AND NON-RETURN TO ZERO (NRZ) [5], [10]- [13] ACROSS THREE TECHNOLOGY NODES.…”

“…Bi-Phase Modulation (BPM) [18] Single Phase Modulation (SPM) [19] Existing State-of-The-Art NRZ [10]- [13] Proposed Approach 2) Bit Error Rate and Latency: The BER of the proposed scheme was then evaluated in each technology using the channel model generated by Ansys HFSS. As shown in Fig.…”

“…17 shows the results of this sweep for two separate test-chips: Chip A (which is assembled with perfect alignment in the inductive channel), and Chip B (which is assembled with an offset of 20 µm in the inductive channel, to demonstrate the effects of stacking misalignment during assembly). At the smallest [18], Single Phase Modulation (SPM) [19], and Non-Return to Zero (NRZ) modulation [10]- [13] benchmark designs at three different technology nodes. Results show improvements between 11.1% and 28.1% using the proposed scheme.…”

“…• A tuneable current driver circuit, to precisely control the Tx energy (within 0.25pJ) depending on the channel quality (and hence compensate for up to 40 µm of dieto-die stacking misalignment in both x and y directions by post-assembly tuning). • Validation of the proposed transceiver using post-layout SPICE simulations in 0.35 µm, 65nm, and 28nm technologies, demonstrating an energy consumption as low as 0.26pJ/bit across a 110 µm channel (a 28% improvement [19], [20] (c) Inductive Non-Return-to-Zero (NRZ) line code (proposed by Miura et al, this is the state-of-the art approach for inductively coupled communication within a 3D-SiP/3D-IC context) [10]- [13]), and (d) The spike-latency encoding scheme proposed in this paper.…”