Electrical Performance of Electronic Packaging
DOI: 10.1109/epep.1997.634037
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The importance of inductance and inductive coupling for on-chip wiring

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Cited by 32 publications
(22 citation statements)
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“…Changing the current by 10 mA in 100 ps on such a wire results in an inductive voltage of 100 mV. Additionally, on medium and long lines, inductive crosstalk between lines can be important (see, e.g., [96]). There is also, of course, significant capacitive coupling and consequent crosstalk between adjacent lines on chips.…”
Section: ) Absence Of Electromagnetic Wave Phenomena (Impedance Matcmentioning
confidence: 99%
See 1 more Smart Citation
“…Changing the current by 10 mA in 100 ps on such a wire results in an inductive voltage of 100 mV. Additionally, on medium and long lines, inductive crosstalk between lines can be important (see, e.g., [96]). There is also, of course, significant capacitive coupling and consequent crosstalk between adjacent lines on chips.…”
Section: ) Absence Of Electromagnetic Wave Phenomena (Impedance Matcmentioning
confidence: 99%
“…There has been considerable recent work, for example, by Deutsch et al [91]- [96] and others [97], examining the effects of inductance, skin effect, and transmission-line effects in wiring on chips. The analysis of on-chip repeatered electrical interconnects was discussed extensively by Bakoglu [98] for the case of lines.…”
Section: B Scaling Of Interconnectsmentioning
confidence: 99%
“…The partial self inductance along the segment is given by (1) where is the magnetic vector potential along segment due to the current in segment , which has a cross section . The partial mutual inductance , which relates the induced voltage drop along segment due to a change in the current along segment , is given by a similar expression (2) In (2), is the magnetic vector potential along segment due to the current in segment and segment has a cross section . The magnetic vector potential is defined as…”
Section: Background and Motivationmentioning
confidence: 99%
“…With higher clocking frequencies and longer global interconnects to span the larger chip dimensions [1] [4], interconnects are sometimes designed and optimized such that inductance effects become evident [2]. The inclusion of inductance in the timing analyses, however, can be a substantial problem for the overall design flows and methodologies.…”
Section: Introductionmentioning
confidence: 99%
“…Inductance effects in on-chip interconnects becomes increasingly important with smaller transition time and lower wire resistance (as a result of copper interconnect), especially in global interconnects such as clock tree, power/ground network, and parallel buses [1]- [3]. Significant inductance causes prominent transmission line effects such as overshoot and undershoot.…”
Section: Introductionmentioning
confidence: 99%