Min/max on-chip inductance models and delay metrics

Lu, Yi-Chang; Celik, M.; Young, Tak; Pileggi, Lawrence T.

doi:10.1145/378239.378506

Cited by 20 publications

(9 citation statements)

References 34 publications

(30 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…5 and Eqn. 6 we can intuitively infer that µ2 and µ3 are always positive when La, Ka = 0, which represents lossy lines with "overdamped" response [14]. Also, µ2 and µ3 decreases monotonically as the self and mutual inductance values increases.…”

Section: Transfer Function Generationmentioning

confidence: 85%

Parasitic aware routing methodology based on higher order RLCK moment metrics

Bhaduri

Vemuri

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

In the multi-GHz frequency domain, inductive and capacitive parasitics of interconnects can cause significant 'ringing' or overdamping, which may lead to false switching or increased delay. Routing techniques which rely on wire length reduction or coupling capacitance minimization are unable to obtain the best routing solution. In this paper, the inductive and capacitive interactions of the wires are introduced through a 'moment' based cost function. This higher order RLCK moment metric guides the routing process of long wires, ensuring that the chosen solution has the best trade-off between ringing and delay under a monotone signal response. Another significant departure from existing routing methodologies is to account for the signal direction in the nets which may increase or decrease the effective inductive and capacitive parasitics.

show abstract

Section: Transfer Function Generationmentioning

confidence: 85%

Parasitic aware routing methodology based on higher order RLCK moment metrics

Bhaduri

Vemuri

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

show abstract

“…Depending on the switching patterns, the difference in loop inductance can be very large; up to 70X in this case. In fact, during in-phase switching the strong positive L m among lines results in an L loop that can be more than 50% larger than L self , which is usually considered as the upper-bound of on-chip inductance [12]. Fig.…”

Section: A Multiple-bit Data-busmentioning

confidence: 99%

Switch-factor based loop RLC modeling for efficient timing analysis

Cao¹,

Yang²,

Huang³

et al. 2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

View full text Add to dashboard Cite

Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on transmission line theory and a switch-factor, which is the voltage ratio between two nets. This switch-factor is also known as the Miller factor and is widely used to model capacitive coupling.The proposed modeling technique can be directly applied to partial RLC netlists extracted using existing parasitic extraction tools without advance knowledge of the return path. The new model accurately captures the impact of neighboring switching activity when it significantly affects the size of current return loop. As demonstrated in our experiments, the new model accurately predicts both upper and lower delay bounds as a function of neighboring switching patterns. Therefore, this approach can be easily implemented into existing timing analysis flows such as max-timing and min-timing analysis. Finally, we apply the new modeling approach to a range of activities across the design process including timing optimization, static timing analysis, high frequency clock design, and data-bus wire planning.

show abstract

“…Even when the mesh structure is adopted, wire inductance still varies according to the relative position inside the mesh grid spacing. The use of analytical formulae for rapid estimation and evaluation of the inductance [6,7], or quantitative evaluation of the inductance impact using statistical methodology have been proposed [8]. However, unknown factors still exist for modeling inductance, such as the contribution of silicon substrate to the current return path.…”

Section: Introductionmentioning

confidence: 99%

Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay

Satō

Masuda²

2005

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip wire delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance.A test chip using 0.13-µm node process is fabricated to demonstrate concept of the iOSC. Four wire structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency global signal lines. The structure with largest inductance variation measured 99 ps delay difference while newly proposing twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. This experiment also provides designers with a guideline for ground density from inductance standpoint. iOSC confirms that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing in high-speed LSI designs.

show abstract

Min/max on-chip inductance models and delay metrics

Cited by 20 publications

References 34 publications

Parasitic aware routing methodology based on higher order RLCK moment metrics

Parasitic aware routing methodology based on higher order RLCK moment metrics

Switch-factor based loop RLC modeling for efficient timing analysis

Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay

Contact Info

Product

Resources

About