This paper proposes an analytical inductance extraction model for characterizing min/max values of typical on-chip global interconnect structures, and a corresponding delay metric that can be used to provide RLC delay prediction from physical geometries. The model extraction and analysis is efficient enough to be used within optimization and physical design exploration loops. The analytical min/max inductance approximations also provide insight into the effects caused by inductances.
A 3D Global Interconnect Parameter ExtractoR(GIPER) has been developed to provide a practical extraction tool for the fill-chip global critical path analysis. It extracts the interconnect parameters (€2, C) of a typical global interconnect within several minutes per net on a Hp 9000/755 workstation within 5% accuracy compared to full 3D numerical simulations.
On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.
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