On-chip inductance modeling of VLSI interconnects

A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A = 2(L(C T + 0.5C)) 1/2 /(R T (C T + C J) + R T C + RC T + 0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.

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On-chip inductance modeling of VLSI interconnects

Cited by 28 publications

References 2 publications

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Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's

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