The International Technology Roadmap of Semiconductors suggests that Quantum Dot Cellular Automata technology might be a possible CMOS substitute. In particular, Magnetic Quantum Dot Cellular Automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and to an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level we propose the use of delay insensitive Null Convention Logic T M (NCL, [1]). It is implemented for magnetic QCA in order to solve the "layout=timing" problem in the specific case of Magnetic QCA. We thus describe an architectural block at system level using a Hardware Description Language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called "snake-clock", proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase "snake-clock" NCL structure works correctly.
Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.
Molecular Quantum Dot Cellular Automata, also called mQCA, are among the most promising emerging technologies for the expected theoretical operating frequencies (THz), the high device densities and the non-cryogenic working temperature. Due to the small size of a mQCA cell, based on one or two molecules, the device prototyping and even a simple circuit fabrication are limited by the lack of control in the technological process. In this paper, we performed an analysis of the possible fabrication defects of a molecular QCA wire built with adhoc synthesized bis-ferrocene molecules. We evaluated the fault tolerance of a real QCA device and accessed its performance in non ideal conditions due to the fabrication criticalities we are facing in our experiments. We achieved these results by defining a new methodology for the fault analysis in the mQCA technology, based both on ab-initio simulations and theoretical computations.The results obtained give quantitative information on the Safe-Operating-Area (SOA) of a bisferrocene molecular wire, and represent an important feedback to improve the technological process for the final experimental set-up.
Quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultra low power consumption and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nano-scale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real time applications with affordable complexity. Low Density Parity Check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes towards overall performance and complexity of LDPC decoder.This work presents a novel QCA architecture for partial parallel, layered LDPC check node. The check node executes Normalized Min Sum decoding algorithm and is flexible to support check node degree dc up to 20. The check node is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area and power dissipation of whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magnetic.
The recently proposed NanoMagnet based Logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility to maintain the information stored without power supply, allows to design low power digital circuits far beyond the limitations of CMOS technology. This work is focused on the key logic block of NanoMagnet based Logic, the Majority Voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance and energy dissipation. Our analysis enables to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using Electron Beam Lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology.
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