New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Santoro, Giulia; Turvani, Giovanna; Graziano, Mariagrazia

doi:10.3390/mi10060368

“…In References [28,29], the authors presented in-memory architectures on which the Advanced Encryption Standard (AES) algorithm was mapped, showing great result in speed and energy saving compared to other solutions. In Reference [1], the authors presented an architecture based on the in-memory paradigm aimed at Convolutional Neural Networks (CNN). The structure is a memory array in which each cell is provided with both storage and computation properties and with the support of an additional weight memory which is designed to support CNN data flow and computation inside the array.…”

Section: Pimmentioning

confidence: 99%

“…But even if the two units are moved very close to each other, they are still distinct components. Others exploited intrinsic functionality of the memory array or slightly modified peripheral circuitry to perform computation.Among the many example provided by literature, one of the best fitting representative of the PIM concept is presented in Reference [1]. In this work the proposed architecture is a memory array in which the cell itself is capable of performing logical operations aimed at solving Convolutional Neural Networks (CNN).…”

mentioning

confidence: 99%

See 1 more Smart Citation

Data Processing and Information Classification—An In-Memory Approach

Andrighetti

¹

,

Turvani

²

,

Santoro

³

et al. 2020

Sensors

Self Cite

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To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that can elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such a system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose a hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.in slow accesses compared to processors computing speed. This discrepancy in performance harms the computing abilities of the CPU, since the memory cannot provide data as quickly as required by the CPU. This problem is called Von Neumann bottleneck or Memory Wall. The idea that took form to solve this problem is to null the distance between processor and memory, removing the cost of data transfer and create a unit which is capable of storing information and of performing operation on them. This idea takes the name of Processing-in-Memory.Many in literature have approached the "in-memory" idea. Some narrowing the physical distance between memory and computation unit by creating and stacking different layers together. But even if the two units are moved very close to each other, they are still distinct components. Others exploited intrinsic functionality of the memory array or slightly modified peripheral circuitry to perform computation.Among the many example provided by literature, one of the best fitting representative of the PIM concept is presented in Reference [1]. In this work the proposed architecture is a memory array in which the cell itself is capable of performing logical operations aimed at solving Convolutional Neural Networks (CNN). In this paper, our main goal is to introduce a proper example of Processing-in-Memory, choosing Bitmap Indexing as an application around which the architecture is shaped. In th...

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“…In [28,29] the authors presented in-memory architectures on which the Advanced Encryption Standard (AES) algorithm was mapped, showing great result in speed and energy saving compared to other solutions. In [1] the authors presented an architecture based on the in-memory paradigm aimed at Convolutional Neural Networks (CNN). The structure is a memory array in which each cell is provided with both storage and computation properties and with the support of an additional weight memory is designed to support CNN data flow and computation inside the array.…”

Section: Pimmentioning

confidence: 99%

“…Among the many example provided by literature, one of the best fitting representative of the PIM concept is presented in [1]. In this work the proposed architecture is a memory array in which the cell itself is capable of performing logical operations aimed at solving Convolutional Neural Networks (CNN).…”

Section: Introductionmentioning

confidence: 99%

Data Processing and Information Classification: An In-Memory Approach

Andrighetti

¹

,

Turvani

²

,

Santoro

³

et al. 2020

Preprint

Self Cite

1

0

View full text Add to dashboard Cite

To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that are able to elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose an hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.

show abstract

Logic‐In‐Memory Characteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure

Shin

¹

,

Son

²

,

Jeon

³

et al. 2023

Adv Elect Materials

1

0

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The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) inverter comprising two R‐FBFETs are investigated. The R‐FBFETs exhibit an extremely low subthreshold swing of ≈1 mV dec−1, a high on/off current ratio of ≈107, and a long retention time of 10 s, owing to a positive feedback loop mechanism. The on‐current ratio of the p‐ to n‐channel modes is 1.03, which indicates a high degree of reconfigurability. The LIM inverter retains the output logic “1” and “0” states for over 50 s under zero‐bias conditions. The symmetric reconfigurable switching and memory operations of the R‐FBFETs enable the LIM inverter to perform logic and memory operations for a long retention time without a power supply.

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New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Cited by 42 publications

References 52 publications

Data Processing and Information Classification—An In-Memory Approach

Data Processing and Information Classification—An In-Memory Approach

Data Processing and Information Classification: An In-Memory Approach

Logic‐In‐Memory Characteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure

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