Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
DOI: 10.1109/cicc.2000.852714
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On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

Abstract: On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.

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Cited by 28 publications
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“…Due to the computer resources required to extract inductances with FastHenry, earlier CAD implementations for superconductive integrated circuits used lookup tabulated results, calculated once with FastHenry, for the inductances of typical structures such as lines, corners, tees and vias [21]; much the same as the technique for semiconductor integrated circuits [25].…”
Section: Inductexmentioning
confidence: 99%
“…Due to the computer resources required to extract inductances with FastHenry, earlier CAD implementations for superconductive integrated circuits used lookup tabulated results, calculated once with FastHenry, for the inductances of typical structures such as lines, corners, tees and vias [21]; much the same as the technique for semiconductor integrated circuits [25].…”
Section: Inductexmentioning
confidence: 99%