Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Park, Jae Hyo; Jang, Gil Su; Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jeong; Lee, Sol Kyu; Joo, Seung Ki

doi:10.1038/srep24734

Cited by 28 publications

(18 citation statements)

References 77 publications

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“…Experimental attempts to demonstrate steep slope operation (that is, S < 60 mV per decade) have focused on two approaches: direct integration of the ferroelectric into the gate stack and external connection of a ferro electric capacitor to a FET [71][72][73][74][75][76] . In the context of NCFETs, organic poly(vinylidenefluoridetrifluoroethylene) gate ferroelectrics [77][78][79] and perovskite PbZr 1−x Ti x O 3 (PZT) gates 80,81 were explored for direct integration, whereas Aurivilliusphase SrBi 2 Ta 2 O 9 (SBT), one of the most popu lar choices for FeFETs and ferroelectric randomaccess memories, appears to have been overlooked. Although perovskite oxides can be directly grown on semiconduc tors 82 , the unfavourable band alignment 83 and interface states at the metal-ferroelectric (M-F) interface usually require the insertion of a dielectric buffer layer, result ing in an MFIS or MFMIS stack (where I and S are the insulating buffer and semiconductor, respectively).…”

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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, which needs to be positive owing to thermodynamic stability. However, this relation is also true if one of the local effective capacitances, for example, C 1 , is negative, as long as the condition C ≥ 0 is fulfilled. In this scenario, the application of an external voltage V results in V int = V(1 + C 2 /C 1) −1 at the interface between the two dielectrics, such that V int /V > 1 if C 1 < 0. That is, NC of one part of the system enables amplification of the voltage at the interface (fig. 1b). Contrary to the usual decrease in the overall capacitance when a regular (positive) capacitance is added in series, the addition of

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Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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“…Specifically, the series structure offers a step-up voltage transformer that brings an abrupt increase in the differential charge of the internal node ( V int ). Accordingly, an NC booster provides an internal voltage amplification ( ∂V int / ∂V gate ), which results in a body factor reduction and a value of SS below the thermal limit of conventional MOSFETs. , …”

Section: Voltage Pinning Effect In Ferroelectric Gate Stacksmentioning

confidence: 99%

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

et al. 2020

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Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

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“…9 Especially recently, the NC effect has been increasingly investigated as it is considered one of the most promising mechanisms for overcoming the limitations of transistors. [10][11][12][13][14] In 2008, S. Salahuddin and S. Datta theorized a low-power nanoscale device that utilizes the ferroelectric NC effect to amplify gate voltage. 7 Continuing experiments on NCFETs over the past 10 years have improved this device.…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Wang

Chen

et al. 2017

npj 2D Mater Appl

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Conventional field-effect transistors (FETs) are not expected to satisfy the requirements of future large integrated nanoelectronic circuits because of these circuits' ultra-high power dissipation and because the conventional FETs cannot overcome the subthreshold swing (SS) limit of 60 mV/decade. In this work, the ordinary oxide of the FET is replaced only by a ferroelectric (Fe) polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)). Additionally, we employ a two-dimensional (2D) semiconductor, such as MoS 2 and MoSe 2 , as the channel. This 2D Fe-FET achieves an ultralow SS of 24.2 mV/dec over four orders of magnitude in drain current at room temperature; this sub-60 mV/dec switching is derived from the Fe negative capacitance (NC) effect during the polarization of ferroelectric domain switching. Such 2D NC-FETs, realized by integrating of 2D semiconductors and organic ferroelectrics, provide a new approach to satisfy the requirements of next-generation low-energy-consumption integrated nanoelectronic circuits as well as the requirements of future flexible electronics.

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Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Cited by 28 publications

References 77 publications

Ferroelectric negative capacitance

Ferroelectric negative capacitance

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

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