Study on characteristics of thermally stable HfLaON gate dielectric with TaN metal gate

Xu, Qing; Xu, Gaobo; Wang, Wenwu; Chen, Dapeng; Shi, Shali; Han, Zhengsheng; Ye, Tianchun

doi:10.1063/1.3050522

Cited by 21 publications

(7 citation statements)

References 7 publications

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“…This observation is in accordance with the deposition sequence, and contributes to a good HfLaON/SiO 2 interface, because Hf is chemically more stable than La when contacting with SiO 2 [5]- [7]. The atomic ratio of La/(La+Hf) in the HfLaON composite film is calculated to be 46 % from the EDS analysis, and this high La content is helpful to keep the HfLaON film amorphous even at a high annealing temperature up to 1000 o C [8]. sample displays higher P/E speeds and larger memory window than the LaON one under the same operating conditions.…”

Section: Results and Disscusionsupporting

confidence: 72%

“…On the other hand, HfON, which shows a smaller dielectric constant (~ 22) than La 2 O 3 (~ 30) [3], [6], is wellknown for its thermodynamic stability with SiO 2 ; consequently, a good interface can be expected between HfON and SiO 2 [6]. Both La 2 O 3 and HfON films present poor thermal stability with a low crystallization temperature; on the contrary, it is widely reported that the HfLaON composite film displays better thermal stability with a higher crystallization temperature than the HfON or La 2 O 3 film [8]. Therefore, based on MONOS capacitors, this work aims to study the charge-trapping characteristics of HfLaON by comparing with nitrided La 2 O 3 .…”

Section: Introductionmentioning

confidence: 96%

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HfON/LaON as charge-trapping layer for nonvolatile memory applications

Huang

Lai

2012

2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC)

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The charge-trapping characteristics of HfON/LaON composite film (denoted as HfLaON) were investigated based on an Al/Al 2 O 3 /HfLaON/SiO 2 /Si (MONOS) capacitor. The physical properties of the high-k film were analyzed by transmission electron microscopy and electron diffraction spectroscopy. Compared with another MONOS capacitor with nitrided La 2 O 3 as charge-trapping layer, the one with HfLaON showed better memory characteristics in terms of larger memory window, higher program speed (6.3 V at +14 V for 100 ȝs), and smaller charge loss (8.2% after 10 4 sec), due to the HfLaON composite film exhibiting an amorphous structure and the suppressed formation of an interlayer at the HfLaON/SiO 2 interface.

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Section: Results and Disscusionsupporting

confidence: 72%

Section: Introductionmentioning

confidence: 96%

HfON/LaON as charge-trapping layer for nonvolatile memory applications

Huang

Lai

2012

2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC)

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“…Currently, nitrided La doped HfO 2 dielectric exhibits the amorphous structure after 1000°C rapid thermal annealing and has a large conduction band offset, which lowers the leakage current. Xu et al have investigated the characteristics of TaN/ HfLaON/SiO x gate stack MOS capacitors with the thinnest EOT of HfLaON gate dielectric down to 0.62 nm [157]. When the ratio of La/Hf + La isnot less than 35%, the thin film remains amorphous at a high temperature up to 1000°C (Fig.…”

Section: Hf-based Oxides Gate Dielectricsmentioning

confidence: 97%

“…Besides HfSiON and HfAlON, HfO 2 film was also alloyed with some other elements, such as Ti, Ta, or La to form HfO 2 -based gate dielectrics [155][156][157][158]. Addition of Ti in Hf oxide can form Hf/Ti-based oxide or oxynitride with higher k value because Ti oxide has higher k value than Hf oxide.…”

Section: Hf-based Oxides Gate Dielectricsmentioning

confidence: 99%

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

134

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“…This was indicative of reduced oxygen vacancy concentration. Xu [37] reported the fabrication of HfLaON gate dielectrics with an EOT of 0.62 nm to suppress tunneling leakage. La doping was demonstrated to enhance the k value of the dielectrics and Alshareef et al [23] observed that the addition of Al into Hf-based high-k materials could passivate the oxygen vacancy 0 V  which induced midgap states but there was with little influence by other aspects of the defects .…”

Section: Dual-dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE. high-k dielectrics, metal gate, interface dipole, MOS stack, effective work function Citation:Huang A P, Zheng X H, Xiao Z S, et al. Interface dipole engineering in metal gate/high-k stacks. Chin Sci Bull, 2012, 57: 28722878, doi: 10.1007/s11434-012-5289-6As poly-Si/SiO 2 is replaced by metal gate/high-k stacks in the 45 nm MOS technological node and beyond, the interface becomes more complicated and there are still many challenges to be solved [1,2], such as the flatband voltage shift (V fb shift) [3]. Hence, the properties of the high-k layer must be reconsidered carefully. It has recently been reported that the interface dipole can induce potential difference across the interface and change the band alignment of the MOS stack, and this phenomenon can be exploited to modulate the V fb shift [4][5][6]. Elemental doping can also improve the performance of the high-k layer. Interface dipole engineering (IDE) by varying the dopants or inserting capping layers has attracted much attention in MOS technology. Not only can this technique control the V fb shift, but also the properties of the high-k dielectrics can be improved [7]. This paper reviews the formation of interface dipole, recent research progresses on IDE and effective work function (EWF) modulation, as well as mechanism of IDE in metal gate/high-k MOS stacks. Interface dipole formation in MOS stackTo control the threshold voltage (V th ), work function of a metal gate should be near the conduction band of Si (~4.3 eV) for nMOS and valence band (~5.2 eV) for pMOS. However, only very few metals can satisfy these requirements and furthermore, when a metal is in contact with the high-k layer, its Fermi-level will tend to be at the neutral level of the high-k layer. This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated. Misra et al. [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al. [11] implanted N into a Mo gate that was

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Study on characteristics of thermally stable HfLaON gate dielectric with TaN metal gate

Cited by 21 publications

References 7 publications

HfON/LaON as charge-trapping layer for nonvolatile memory applications

HfON/LaON as charge-trapping layer for nonvolatile memory applications

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Interface dipole engineering in metal gate/high-k stacks

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