SRAM-based NBTI/PBTI sensor system design

Qi, Zhenyu; Wang, Jiajing; Cabe, Adam C.; Wooters, Stuart N.; Blalock, Travis N.; Calhoun, Benton H.; Stan, Mircea R.

doi:10.1145/1837274.1837486

Cited by 26 publications

(9 citation statements)

References 12 publications

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“…The sensor proposed in [15] perfectly fits our needs: it can be easily embedded into an existing memory array and it is extremely compact. The sensor is in fact an asymmetric 6T SRAM cell with one of the two pMOS designed stronger than the other.…”

Section: Architectural Supportmentioning

confidence: 76%

Aging-aware caches with graceful degradation of performance

Mahmood¹,

Poncino²,

Loghi³

et al. 2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Aging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologies. Without any countermeasure, the first component which becomes unreliable will determine the life span of an entire device. This problem is even more relevant for memory arrays, where failure of a single SRAM cell would cause the failure of the whole system. Traditional implementation of power management by turning idle cache lines into a low-energy state can also mitigate the aging effects caused by Negative Bias Temperature Instability (NBTI) provided that idleness is correctly exploited.In this work, we propose a cache structure which deals with cell failures by gracefully degrading its performance. By this partitioning-based strategy, various sub-blocks will become un reliable at different times, and the cache will keep functioning with reduced efficiency. Coupling such aging mitigation with the resulting energy reduction techniques we can obtain up to 2.5x lifetime extension and 40% energy savings with respect to a power managed cache.

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Section: Architectural Supportmentioning

confidence: 76%

Aging-aware caches with graceful degradation of performance

Mahmood¹,

Poncino²,

Loghi³

et al. 2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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“…In order to evaluate the time zero variation and aging status (V T value) of the SRAM cells in a cache memory array, an on chip monitoring circuit is required [16,17,18]. In this work, we propose a monitoring approach that can measure the BTI wearout of the individual SRAM memory cells in each memory column, which also considers the process variation among the SRAM cells.…”

Section: Aging Monitor In Sram Cellsmentioning

confidence: 99%

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Pouyan

Amat

Barajas

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.

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“…7 is particular to the given technology employed and needs to be uniquely characterized for any new technology to determine the required trigger point. The methodology to generate and characterize such curves is presented in [23]. The trigger point can be calculated as shown in (2), where is the pMOS size ratio (1.1 in Fig.…”

Section: B Reaching the System Trigger Pointmentioning

confidence: 99%

“…In statistics, the notion of confidence intervals is used to determine these error rates. We previously derive a method for calculating such confidence intervals, as is shown here in (3) [23] (3) Equation (3) calculates the probability of the system triggering, given a certain number of sensors , initial current means and , deviations and , and current degradation rates and . These values are determined through simulation in this work.…”

Section: Area Analysis and System Error Ratesmentioning

confidence: 99%

Tracking On-Chip Age Using Distributed, Embedded Sensors

Wooters

Cabe

et al. 2012

IEEE Trans. VLSI Syst.

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Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by contributing a sensing scheme that employs on-chip sensors capable of accurately tracking NBTI pMOS current degradations across process, temperature, and varying activity factors. Results show that a 7600 m sensing area achieves an overall system accuracy of 90% at a voltage threshold precision of 2 mV. We thoroughly describe the sensor design and the underlying statistics used to determine overall accuracy and precision. Furthermore, a novel sensor distribution method is presented that uses an existing scan-chain methodology to mask the overhead of adding the on-chip sensors.

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SRAM-based NBTI/PBTI sensor system design

Cited by 26 publications

References 12 publications

Aging-aware caches with graceful degradation of performance

Aging-aware caches with graceful degradation of performance

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Tracking On-Chip Age Using Distributed, Embedded Sensors

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