Tracking On-Chip Age Using Distributed, Embedded Sensors

Abstract

Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by contributing a sensing scheme that employs on-chip sensors capable of accurately tracking NBTI pMOS current degradations across process, temperature, and varying activity factors. Results show that a 7600 m sensing area achieves an overall system accuracy of 90% at a voltage threshold precision of 2 mV. We thoroughly describe the sensor design and the underlying statistics used to determine overall accuracy and precision. Furthermore, a novel sensor distribution method is presented that uses an existing scan-chain methodology to mask the overhead of adding the on-chip sensors.

Fine grained wearout sensing using metastability resolution time

“…In 32nm technology, this translates into 105μm 2 excluding routing overhead. Although this is significantly large compared to a single sensor area in [11], our proposed wearout sensor is tolerant to process variation and does not require multiple instantiations. Further, a single sensor can provide finer resolution measurement.…”

“…A hybrid sensor is proposed in [10], using a combination of RO and vernier delay measurement providing high resolution and faster wearout measurement. In [11], Wooters propose a small embedded NBTI sensor using metastable element. The lightweight sensors use resolution state of mismatched crosscoupled inverters to detect device degradation.…”

“…While techniques such as the ones proposed in [9] and [10] target high precision wearout sensing, [11] implements small area sensors using metastable circuit. The fundamental sensor circuit consists of a pair of cross coupled inverters.…”