Conversion of the Reed-Muller (RM) expansion between two different polarities is an important step in the synthesis and optimization of RM circuits. By investigating XOR decomposition, a new conversion algorithm is proposed to convert MPRM expansion from one polarity to another. First, the relationship between XOR decomposition and mixed polarity is set up. Second, based on this, the operation relation of term coefficients between the two polarities is derived to realize MPRM expansion conversion. And finally, with the MCNC Benchmark, the results of our algorithm show that it is more suitable for dealing with MPRM expansion with more terms. Compared to the previous tabular technique, the conversion efficiency is improved up to approximately 44.39%.
As the underwater acoustic channel is timefrequency variable, the synchronization plays an important role in whole communication. In this paper, the tradition signal of LFM (linear frequency modulation) is taken as the synchronization signal, and a flexible technique method to detect LFM signal are proposed with little resources. Compared to the basic one, the optimized structure uses the multiple-cycle technology to finish computation. Also the detail design and implement results with FPGA (Field Programmable Gate Array) will be given, and it is verified by simulation and field data that the method is feasible.
Polarity optimization for mixed polarity Reed-Muller (MPRM) circuits is a combinatorial issue. Based on the study on discrete particle swarm optimization (DPSO) and mixed polarity, the corresponding relation between particle and mixed polarity is established, and the delay-area trade-off of large-scale MPRM circuits is proposed. Firstly, mutation operation and elitist strategy in genetic algorithm are incorporated into DPSO to further develop a hybrid DPSO (HDPSO). Then the best polarity for delay and area trade-off is searched for large-scale MPRM circuits by combining the HDPSO and a delay estimation model. Finally, the proposed algorithm is testified by MCNC Benchmarks. Experimental results show that HDPSO achieves a better convergence than DPSO in terms of search capability for large-scale MPRM circuits.
As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 298.94 m 2 . After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.
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