Aging-aware caches with graceful degradation of performance

Abstract

Aging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologies. Without any countermeasure, the first component which becomes unreliable will determine the life span of an entire device. This problem is even more relevant for memory arrays, where failure of a single SRAM cell would cause the failure of the whole system. Traditional implementation of power management by turning idle cache lines into a low-energy state can also mitigate the aging effects caused by Negative Bias Temperature Instability (NBTI) provided that idleness is correctly exploited.In this work, we propose a cache structure which deals with cell failures by gracefully degrading its performance. By this partitioning-based strategy, various sub-blocks will become un reliable at different times, and the cache will keep functioning with reduced efficiency. Coupling such aging mitigation with the resulting energy reduction techniques we can obtain up to 2.5x lifetime extension and 40% energy savings with respect to a power managed cache.

Cache aging reduction with improved performance using dynamically re-sizable cache

“…At the end of its normal lifetime, i.e., as soon as the first unit of access (a line) fails, instead of discarding whole cache, we only discard that specific portion (block) of the cache containing that line. This is the basic principle of the partitioned cache for aging, used in [3], [4]. The difference between the traditional partitioned architectures and our modified DRC lies in how the "dead" block is managed.…”

“…In the partitioned approach the dead portion of the cache is marked as invalid, with the result that subsequent accesses to lines in that block will systematically result into a miss. This is why the approaches of [3], [4] suffer from a significant deterioration of performance after the first block fails. In the proposed architecture, conversely, once a block becomes unusable, we resize the cache according to the DRC principle and then cache is flushed and re-configured to work as a smaller size cache.…”

“…To this purpose, we utilize the concept presented in [3], [4] for Average Miss Rate (AMR), which measures the performance of the cache by calculating average level of service offered over time and Effective LifeTime (ELT) defined as the product of lifetime and size of a memory block. It conceptually measures for how much time a memory block of a given size can be used.…”