SOI bulk and surface generation properties measured with the pseudo-MOSFET

Kang, Sung-Won; Schroder, D.K.

doi:10.1109/ted.2002.803639

Cited by 33 publications

(8 citation statements)

References 16 publications

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“…It is known that surface passivation is enhanced by the presence of an electric field. 15 This is because driving the interface in strong inversion or accumulation strongly unbalances the electron and hole concentrations, thus reducing the probability of recombination.…”

Section: Soi With Alumina Box-mentioning

confidence: 99%

UTBOX SOI Substrate with Composite Insulating Layer

Landru

Allibert

Daval

et al. 2013

ECS J. Solid State Sci. Technol.

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Ultra thin body and Buried Oxide (BOX) SOI substrates are of high interest for the fabrication of high performance CMOS Fully Depleted (FD) devices. We have investigated the fabrication of SOI wafers with an Ultra Thin alumina BOX (UTBOX). 300 mm SOI substrates with composite SiO 2 / Alumina / SiO 2 buried insulating layer have been manufactured using industrial Smart Cut TM technology and a BOX dissolution stage. The substrates quality is in line with standard UTBOX products in terms of layers morphology, defectivity and thickness uniformity. It is shown that the thin SiO 2 capping layers prevent the collapse of the alumina layer at high temperature and bring excellent BOX/silicon interface electrical quality with low D IT and good carrier mobility. The alumina layer exhibits a stable embedded negative charge of 3 × 10 12 cm −2 and a low EOT according to its high permittivity. These unique properties make composite BOX substrates especially interesting for charge trapping applications or in FD devices manufacturing where alumina can act as an embedded etch stop layer.Fully Depleted (FD) devices provide the electrostatic boost that is required to manufacture CMOS technology with printed gate lengths 25 nm and below, with the additional benefit of improved variability due to the ability of these devices to operate with undoped channel. Two embodiments of FD devices are developed: 3D Multi Gate 1 and planar FDSOI. 2,3 Both deliver on expectations with demonstration of great DIBL at extremely scaled gate lengths that translate into superior performance especially at reduced Vdd. SOI substrates will play a major role in these new technologies. They greatly simplify the 3D FET process and reduce device variability. Planar Fully-Depleted technology has already been demonstrated on SOI wafers with UltraThin Body and BOX (UTBB) with very high energy efficiency, 4 and is entering production at the 28 nm node.The extremely thin BOX option provides additional characteristics: it further improves the electrostatics of the devices, 5 it allows dynamic change of the Vt through back biasing 6 and enables SOI/Bulk hybrid integration. 7 Further scaling the FDSOI technology requires improving the electrostatic control. One relevant knob to reduce the short-channel effects is to increase the back-gate to channel coupling. This can be achieved by using a thinner BOX and/or by resorting to a high-k dielectric.The novel composite SiO 2 /Al 2 O 3 /SiO 2 BOX SOI substrates studied in this paper have a higher BOX permittivity than pure SiO 2 allowing for better capacitive coupling at the same physical thickness, while maintaining low D IT (Interface Trap Density) with good interface carrier mobility.Moreover, the powerful etch stop capability of the alumina inserted in the BOX enables MESA isolation in a CMOS flow. This can be applied for planar or FinFET technologies.Combination of those two effects brings significant advantages in terms of integration, increasing the manufacturing process window. SOI with alumina BOX.-The use of alumin...

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Section: Soi With Alumina Box-mentioning

confidence: 99%

UTBOX SOI Substrate with Composite Insulating Layer

Landru

Allibert

Daval

et al. 2013

ECS J. Solid State Sci. Technol.

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“…Usually, the generation lifetime measurement methods are using long channel devices, because in the analysis the source/drain junction contribution to the generation lifetime is not considered (15). Other techniques, that can also be applied in short channel SOI devices, require that one silicon surface is kept in strong accumulation and the other in inversion (1,2,18) or they need special structures (19,20) for extracting the generation parameters. An improvement of the standard model for the hole generation lifetime extraction of reference (5), that considers the influence of the halo implanted region and of the channel length reduction was published in reference (21).…”

Section: Ecs Transactions 50 (5) 225-236 (2012)mentioning

confidence: 99%

(Invited) Transistor-Based Extraction of Carrier Lifetime and Interface Traps Densities in Silicon-on-Insulator Materials

et al. 2013

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This paper presents the main transistor-based extraction methods for the carrier lifetime and the interface trap density in Silicon-OnInsulator materials. The device/technology under analysis begins with the partially-depleted SOI MOSFET, following by the fully depleted SOI with ultra-thin buried oxide (UTBOX) devices. The results show that the major part of the method may be extended but requires some careful analysis/interpretation and sometime a correction factor.

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“…The pseudo MOSFET (Ψ-MOSFET) is a simple, yet powerful, device to characterize various aspects of SOI wafers and is routinely used for incoming wafer inspection to determine material parameters (3)(4)(5)(6)(7). It comes in the point contact and the mercury probe (HgFET) configurations.…”

Section: Advantages and Fabrication Of Gsg Pseudo Mosfetmentioning

confidence: 99%

“…Motivation for Ground-Signal-Ground Ψ-MOSFET Attempts to measure LFN of point contact Ψ-MOSFETs have not been successful because of repeatability problems. It has not been possible to place the point probes consistently on the same spots and apply the same pressure (6). Thus the results have had significant variance from one measurement to the next one with the same operating point.…”

Section: Advantages and Fabrication Of Gsg Pseudo Mosfetmentioning

confidence: 99%

SOI Low Frequency Noise and Interface Trap Density Measurements with the Pseudo MOSFET

et al. 2006

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Low frequency noise (LFN) is important in analog and digital circuits. In analog circuits it affects the performance of low- noise amplifiers and the phase noise of voltage-controlled oscillators. In digital circuits it becomes more important as the supply voltage is reduced and it degrades substrate noise coupling. Low-frequency noise is due to interactions of the channel carriers with oxide/semiconductor interface traps and oxide charges and is very dependent on the quality of the oxide/semiconductor interface and noise measurements can give important information about such interfaces and defects (1). Silicon-on-insulator devices have two oxide/semiconductor interfaces and the bottom interface is generally worse than the top interface. Most LFN measurements are made after MOSFET fabrication, but it is desirable to characterize such materials without fabricating devices. In this paper we discuss silicon- on-insulator (SOI) low-frequency noise and interface trap density measurements using a Ground-Signal-Ground (GSG) pseudo- MOSFET structure with minimum fabrication.

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SOI bulk and surface generation properties measured with the pseudo-MOSFET

Cited by 33 publications

References 16 publications

UTBOX SOI Substrate with Composite Insulating Layer

UTBOX SOI Substrate with Composite Insulating Layer

(Invited) Transistor-Based Extraction of Carrier Lifetime and Interface Traps Densities in Silicon-on-Insulator Materials

SOI Low Frequency Noise and Interface Trap Density Measurements with the Pseudo MOSFET

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