UTBOX SOI Substrate with Composite Insulating Layer

Abstract

Ultra thin body and Buried Oxide (BOX) SOI substrates are of high interest for the fabrication of high performance CMOS Fully Depleted (FD) devices. We have investigated the fabrication of SOI wafers with an Ultra Thin alumina BOX (UTBOX). 300 mm SOI substrates with composite SiO 2 / Alumina / SiO 2 buried insulating layer have been manufactured using industrial Smart Cut TM technology and a BOX dissolution stage. The substrates quality is in line with standard UTBOX products in terms of layers morphology, defectivity and thickness uniformity. It is shown that the thin SiO 2 capping layers prevent the collapse of the alumina layer at high temperature and bring excellent BOX/silicon interface electrical quality with low D IT and good carrier mobility. The alumina layer exhibits a stable embedded negative charge of 3 × 10 12 cm −2 and a low EOT according to its high permittivity. These unique properties make composite BOX substrates especially interesting for charge trapping applications or in FD devices manufacturing where alumina can act as an embedded etch stop layer.Fully Depleted (FD) devices provide the electrostatic boost that is required to manufacture CMOS technology with printed gate lengths 25 nm and below, with the additional benefit of improved variability due to the ability of these devices to operate with undoped channel. Two embodiments of FD devices are developed: 3D Multi Gate 1 and planar FDSOI. 2,3 Both deliver on expectations with demonstration of great DIBL at extremely scaled gate lengths that translate into superior performance especially at reduced Vdd. SOI substrates will play a major role in these new technologies. They greatly simplify the 3D FET process and reduce device variability. Planar Fully-Depleted technology has already been demonstrated on SOI wafers with UltraThin Body and BOX (UTBB) with very high energy efficiency, 4 and is entering production at the 28 nm node.The extremely thin BOX option provides additional characteristics: it further improves the electrostatics of the devices, 5 it allows dynamic change of the Vt through back biasing 6 and enables SOI/Bulk hybrid integration. 7 Further scaling the FDSOI technology requires improving the electrostatic control. One relevant knob to reduce the short-channel effects is to increase the back-gate to channel coupling. This can be achieved by using a thinner BOX and/or by resorting to a high-k dielectric.The novel composite SiO 2 /Al 2 O 3 /SiO 2 BOX SOI substrates studied in this paper have a higher BOX permittivity than pure SiO 2 allowing for better capacitive coupling at the same physical thickness, while maintaining low D IT (Interface Trap Density) with good interface carrier mobility.Moreover, the powerful etch stop capability of the alumina inserted in the BOX enables MESA isolation in a CMOS flow. This can be applied for planar or FinFET technologies.Combination of those two effects brings significant advantages in terms of integration, increasing the manufacturing process window. SOI with alumina BOX.-The use of alumin...

Direct Bonding Mechanism of ALD-Al2O3Thin Films

“…It was demonstrated that Al 2 O 3 thick films are poor oxygen barriers especially in their amorphous states, suggesting that a silicon oxidation happens at deposition interface. 21 It is also reported that 18 O diffusion into crystallized γ-Al 2 O 3 films was limited to about 10 nm while oxygen could diffuse throughout the full amorphous layer. Based on this scenario, and Nabatame et al study, crystallization of alumina thin film thicker than 10 nm is enough to create oxygen barrier, limit silicon oxidation and therefore blistering generation.…”

“…If we refer to literature to link annealing temperature or atmosphere to chemical phenomena we found that Landru et al suggest unfavorable evolution of alumina/silicon interface with temperature. 18 It is also known that SiO 2 growth at deposition interface can be observed during annealing. 19,20 Indeed, Copel et al have observed that a growth of interfacial SiO 2 layers takes place during low-pressure oxidation at 600 • C. 19 It's interesting to note that at this temperature, blistering appears in our annealing condition.…”

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

“…3, could mean that UTBB devices with very small BOX thickness, that may include passivated negative interface traps, could provide interesting postirradiation characteristics. Therefore, alumina BOX and composite SiO 2 /alumina UTBOX transistors such as those reported in [36] (Fig. 4) are very interesting for examination.…”

“…These devices feature a BOX of 25 nm down to a few nanometer that, when combined with UTB, results in very good electrostatic control of the gate and reduced variability originating from RDF effects [32]- [36]. UTB and BOX (UTBB) device performance is enhanced compared to extremely thin SOI (ETSOI) [37], both in terms of short channel effect control and S/D coupling due to the use of the thin BOX, and especially when combined with a ground plane doping scheme [38].…”

Ультратонкие Скрытые Стеки Оксидов Гафния И Алюминия В Полевых Структурах Кремний-На-Изоляторе / Попов В.П., Антонов В.А., Ильницкий М.А., Мяконьких А.В., Руденко К.В.

“…Чтобы избежать подобных дефектов в структурах типа UTBB SOI было предложено использовать вместо диоксида кремния более толстый диэлектрик с высокими теплопроводностью и диэлектрической постоянной (high-k) [2]. Минимальное значение EOT = 7.9 нм было получено для стека с аморфным Al 2 O 3 из-за относительно толстых слоев SiO 2 , нанесенных для достижения низкой плотности состояний (interface states -IFS) на гетерогранице Si/SiO 2~ 5x10 11 eV −1 cm −2 .…”