(Invited) Transistor-Based Extraction of Carrier Lifetime and Interface Traps Densities in Silicon-on-Insulator Materials

Martino, João Antônio; Sonnenberg, Victor; Galeti, Milene; Aoulaiche, M.; Simoen, Eddy; Claeys, Cor

doi:10.1149/05005.0225ecst

Cited by 7 publications

(2 citation statements)

References 21 publications

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“…The gate electrode considered has a metal work function around 4.53 eV (TiN). Interface traps were considered in the simulations with N itf =N itb =2x10 11 eV -1 cm -2 [23]. UTBB SOI nMOSFETs with a substrate doping concentration of Na SUB =10 18 and 10 15 cm -3 were used to simulate devices with and without GP, respectively.…”

Section: Measurement and Simulation Detailsmentioning

confidence: 99%

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Itocazu¹,

Sonnenberg²,

Martino³

et al. 2020

JICS

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This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

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Section: Measurement and Simulation Detailsmentioning

confidence: 99%

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Itocazu¹,

Sonnenberg²,

Martino³

et al. 2020

JICS

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“…7 eV (TiN). Interface traps were considered in the simulations [4] and in this work with NitFNitb=2xlO ll eV-1 cm-Z . UTBB SOl nMOSFETs with a substrate doping concentration of NasuB=10 18 and 10 15 cm-3 were used to simulate devices with and without GP, respectively.…”

Section: Experimental Devicementioning

confidence: 99%

Influence of high temperature on substrate effect of UTBB SOI nMOSFETs

Itocazu

Sonnenberg

Simoen

et al. 2014

2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)

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An analysis of the temperature influence on the substrate effect of short channel Ultra Thin Body and BOX (UTBB) SOl nMOSFETs with and without Ground Plane (GP) implantation is presented. This study was done from room temperature up to 200·C. The theoretical model was applied and the results are in agreement with experimental and simulation data. The data shows a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop over the gate and buried oxides. The maximum difference between V GB with and without GP decreases for high temperature.

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