Rigorous analysis of two-level charge pumping: Application to the extraction of interface trap concentration versus energy profiles in metal–oxide–semiconductor transistors

Abstract

Charge pumping (CP) is the most widely used Si−SiO2 interface trap electrical characterization technique. However, several important characteristics and basic principles of this technique have not yet been rigorously defined. In this article, the onsets of nonsteady-state carrier emission and steady-state carrier capture, which occur during the transition edges of the gate signal when large gate pulses are used, are defined. The energies at the Si−SiO2 interface where these mechanisms start are calculated. Then, the case of asymmetrical or of small gate pulses, where capture of at least one carrier type cannot occur during the transition edges of the gate signal but proceeds during the following steady-state bias, is dealt with. The consequences of such a situation on the contribution of carrier emission to the CP current is studied. This allows a model which accurately describes the CP current in a large number of situations to be obtained. Using this model, it is shown that when the trap capture cross sections are small near the band edges, the energies where non-steady-state carrier emission takes place, interact with the high and/or low Fermi-level position. It is also shown that under asymmetrical biases, the energy regions in the upper and lower half of the band gap contributing to the CP current vary nearly symmetrically. This model is used for discussing the reliability of two-level CP for extracting interface trap concentration versus energy, Dit(E), profiles in metal–oxide–semiconductor devices. A comparison is carried out with the simplified extraction methods found in literature. The influence, on the Dit(E) profiles, of the trap cross sections and of the biases is discussed. The advantages of the spectroscopic CP are pointed out.

Advanced Analysis of Silicon Insulator Interface Traps in MOSFET's with SiO2 and HfO2 as Gate Dielectrics

“…The results presented in the preceding support that at the Si-SiO 2 interface in fully processed S-A MOSFET's two trap distributions dominate in the energy region probed by two-level CP, i.e. 0.6 to 0.8 eV depending on the capture cross section of the traps (59). The corresponding traps are likely located at the interface.…”

“…11, their different right hand edges superimpose, due to the fact that there, as (E i -E l ) < (E h -E i ), the low Fermi level, E l , fully controls the CP signal (Fig. 28a) (44,56,59). In Fig.…”

“…6, these two contributions enable the simulations of the whole CP curves regardless of V sw . In such conditions, and depending on the trap capture cross sections, the energy region probed at the interface is comprised between 0.6 and 0.8 eV (59).…”

Do NBTI-induced interface states show fast recovery? A study using a corrected on-the-fly charge-pumping measurement technique

“…As illustrated in Fig. 1, the basic difference between OFIT and CCP [9][10][11][12] is that the low-level V G,low of the CP pulse is simultaneously used as a stress condition (for NBTI), while the actual CP measurement is performed by quickly switching back and forth between accumulation Vacc and stress Vstress. Consequently, an issue we will get back to later, the low-levels are different during stress and recovery/reference measurements.…”

Modeling Stressed MOS Oxides Using a Multiphonon-Assisted Quantum Approach—Part II: Transient Effects

“…Fig. 8 illustrates the simulated f CP for three frequencies (1 kHz, 10 kHz, and 1 MHz) at T = 300 K and V sw = 2.5 V. The maximum probed regions achievable are illustrated at V low cor- [5], [15], [16], [23]. responding to the maximum CP current.…”