Reliability characterization and FEM modeling of power devices under repetitive power pulsing

Abstract

In this work a combined experimental/numerical approach to describe the thermo-mechanical behavior of power devices under repetitive power pulsing is presented. Stress tests have been carried out on power DMOS implemented in Smart Power BCD technology with different Back-End Of Line (BEOL) schemes, including, for the first time, full Copper. Mechanical laboratory nano-indentation tests have been used to determine constituent properties of the metal layers. Thermo-mechanical 3D FEM modeling has been used to simulate a multi-cycle thermal loading of a whole power device with its package. Results from simulation have been qualitatively compared to experimental results. © 2013 IEEE

Low-cycle fatigue of multilayer metal stack employed as fast wafer level monitor for backend integrity in smart power technologies

“…Here level of intrinsic robustness decides if the test may be implemented as an end-of-life test with feedback on systematic trends and homogeneity, as we demonstrated by a case-study, or if it may be implemented as a pass/fail test which nevertheless will flag impaired integrity of backend stack. For state-ofthe-art smart-power technologies with modular backend options we expect the latter to apply in particular if thin AlCu levels or dual-damascene-copper levels are employed [4].…”

“…Here the RPP failure mechanism active in a low-cycle fatigue regime may be assumed as follows: The large thermal swing leads to high lateral mechanical stress states beyond the yield point of the metal thin films such that each cycle may accumulate a viscoplastic deformation of the metal. Ultimately stress on dielectrics may exceed critical limits and an electrical detectable leakage path or even short in the drain/source metal path of the driver results [3,4,5]. We checked by failure analysis, that DUT failure indeed is caused by shorts in metal system and is unrelated to Si active device.…”

“…Each switching cycle can involve a millisecond power pulse leading to a pronounced local temperature excursion in the driver stage. A strong lateral temperature gradient imposes severe stress on the IC backend structures due to the mismatch of the coefficient of thermal expansion of aluminum or copper metals and dielectrics which may cause degradation and IC failure in respective applications [1,2,3,4,5]. Compared to vertical discrete power devices, where cyclic thermomechanical stress leads to pronounced aging of the usually thicker top aluminum metal layer itself [6], for smart-power IC products additional failure channels are present related to dielectrics and various interfaces in the fine-combed multifinger metal stack.…”

Reliability characterization of power devices which operate under power cycling

“…In addition, we showed in [3] that the reliability is highly affected by the temperature distribution (temperature gradients). The reliability of power devices can be improved by optimizing the layout of the DMOS metallization system [4], by using materials with better thermal/mechanical properties [5][6] or by controlling both the peak temperature and the temperature gradient in the device [3].…”

Experimental Reliability Improvement of Power Devices Operated Under Fast Thermal Cycling

“…The problem is usually solved by careful design of the DMOS metallization structure, (e.g. optimizing the distances between metal lines [4]) and by other materials and technology related solutions [5], [6]. The disadvantage of the latter is that, sometimes, production costs are traded for better robustness.…”