Power islands: a high-level synthesis technique for reducing spurious switching activity and leakage

Dal, Deniz; Kutagulla, D.; Nunez, A.; Mansouri, N.

doi:10.1109/mwscas.2005.1594490

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…Voltage islands (VIs), a power consumption reduction technique we employed in this study, can also be effective in minimizing the circuit power leakage and spurious switching activity (SSA). 29 SSA can occur in circuits in which resources (functional units or registers) have more than one task or variable bound to it, which results in different values being output in different clock cycles. This can affect other parts of the circuit if not properly handled.…”

Section: Related Workmentioning

confidence: 99%

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Dilek,

Tosun,

Cakin

2023

Circuit Theory & Apps

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SummaryIntegrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error‐prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy‐based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High‐level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi‐objective optimization problem of finding a set of Pareto‐optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)‐based HLS methods for multi‐Vcc application‐specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)‐based and integer linear programming (ILP)‐based methods and showed their effectiveness in finding optimum or near‐optimum results in a short running time. SA‐based methods achieved up to 21.20% reliability improvement on average and up to 38% energy reduction on average, while preserving the reliability value against the GA‐based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.

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Section: Related Workmentioning

confidence: 99%

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Dilek,

Tosun,

Cakin

2023

Circuit Theory & Apps

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“…PIS is a novel HLS methodology that eliminates the Spurious Switching Activity (SSA) and the leakage in a great portion of the resulting circuit by partitioning it into islands [4], [3]. Each Island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and can be completely powered down when all the logic it contains is idling.…”

Section: Power Islands Synthesis (Pis)mentioning

confidence: 99%

A high-level register optimization technique for minimizing leakage and dynamic power

Dal

Mansouri

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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A large fraction of the total power dissipated in a digital circuit is consumed by the clocked elements in the data-path. Hence, savings in power usage of these components can be directly reflected in a circuit's overall power consumption. Reducing power through techniques that optimize power consumption in combinational elements has been extensively discussed in the existing literature. However, these techniques cannot be applied for reducing the power in sequential elements. In this work, we focus on this problem, and introduce a novel cluster-based register optimization technique that is employed in High-Level Synthesis (HLS) with Power Islands. Our experiments conducted on several synthesis benchmarks implemented at the transistor level using a 65 nm process technology showed an average reduction of 18% in total power consumption due to our technique with no or little area overhead.

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“…Therefore, a method that can amass information from sources and reduce this to a simple set of rules for scheduling would be highly desirable. Work on energy harvesting has tended to investigate the modeling aspect used [3,4] or optimization of the logic within the processor [5,6], often with complicated management systems defined. These systems can consume more energy than they save in extreme cases, therefore a simple, logical approach to energy harvesting would he highly desirable.…”

Section: Introductionmentioning

confidence: 99%

Identification of Key Energy Harvesting Parameters through Monte Carlo Simulations

Docherty

Bystrov

Yakovlev

2012

2012 UKSim 14th International Conference on Computer Modelling and Simulation

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As the number of embedded systems increases, so do the demands placed upon them. Current algorithms are capable of creating adequate schedules under ideal conditions, but can be considered inadequate when many variables must be regarded. End users are demanding ever greater performance while minimizing failures and power consumption, meaning advanced power management must be incorporated into circuit designs; especially in multi-core environments. This paper summarizes the initial investigation into the simulation of an energy harvesting system to identify key parameters. This is done by initial multi-vary analysis to determine primary contributors, which are then refined through Design of Experiments (DoE). Finally, the reduced model is subject to control through Statistical Process Control (SPC) to confirm whether monitoring causes a statistical difference to the output reliability and if so, what parameter has the greatest effect.

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Power islands: a high-level synthesis technique for reducing spurious switching activity and leakage

Cited by 6 publications

References 6 publications

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

A high-level register optimization technique for minimizing leakage and dynamic power

Identification of Key Energy Harvesting Parameters through Monte Carlo Simulations

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