A high-level register optimization technique for minimizing leakage and dynamic power

Abstract

A large fraction of the total power dissipated in a digital circuit is consumed by the clocked elements in the data-path. Hence, savings in power usage of these components can be directly reflected in a circuit's overall power consumption. Reducing power through techniques that optimize power consumption in combinational elements has been extensively discussed in the existing literature. However, these techniques cannot be applied for reducing the power in sequential elements. In this work, we focus on this problem, and introduce a novel cluster-based register optimization technique that is employed in High-Level Synthesis (HLS) with Power Islands. Our experiments conducted on several synthesis benchmarks implemented at the transistor level using a 65 nm process technology showed an average reduction of 18% in total power consumption due to our technique with no or little area overhead.