This paper summarizes the design of a reprogrammable Application Specific Integrated Circuit capable of performing all members of the Secure Hash Algorithm (SHA) group of Hash Functions. The need for high-speed cryptography is introduced, as well as the SHA-1 and SHA-2 Hash Functions and their operation. Work performed at other institutions to improve throughput and power consumption is presented with advantages and disadvantages discussed. The ASIC design is then discussed, with comparisons made to previously published ASIC and FPGA implementations. The possibility of using this ASIC architecture for the SHA-3 candidates, as well as the Message Digest (MD) families of Hash Functions is suggested as an area of future work as it is shown the ASIC Architecture designed would be capable of this with only program modifications required.
As the number of embedded systems increases, so do the demands placed upon them. Current algorithms are capable of creating adequate schedules under ideal conditions, but can be considered inadequate when many variables must be regarded. End users are demanding ever greater performance while minimizing failures and power consumption, meaning advanced power management must be incorporated into circuit designs; especially in multi-core environments. This paper summarizes the initial investigation into the simulation of an energy harvesting system to identify key parameters. This is done by initial multi-vary analysis to determine primary contributors, which are then refined through Design of Experiments (DoE). Finally, the reduced model is subject to control through Statistical Process Control (SPC) to confirm whether monitoring causes a statistical difference to the output reliability and if so, what parameter has the greatest effect.
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