Performance Analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap

Mudidhe, Praveen Kumar; Nistala, Bheema Rao

doi:10.1109/ises54909.2022.00068

Cited by 5 publications

(3 citation statements)

References 19 publications

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“…The gate near the source end is known as control gate and gate near drain end is referred as screen gate. Moreover, the DM gate generates a step like potential in the channel region, thereby the electric field increases at interface of gate metals resulting in increase of drain current [19,20]. For a traditional MOSFET, the electric field is weak closer to the source side and increases dramatically as it approaches the drain.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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“…There are different methods like material, gate and channel engineering to enhance the efficiency of the CGAA FET. 5 In gate engineering, a metal gate with two different work functions are utilized having lower and higher work functions at drain and source side respectively, whereas in channel engineering, two different doping concentrations, source side with higher doping concentration and drain side with lower doping concentration 6 is used. Due to dual material gate, development of the step potential occurs in the channel that leads to enhancement of carrier transport and thereby suppresses the hot carrier effect.…”

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confidence: 99%

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

Mudidhe

Nistala

2023

ECS J. Solid State Sci. Technol.

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This manuscript introduces a pioneering investigation on the temperature effects of Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET by outlining its significance in various aspects such as analog/RF, self-heating, and linearity performance metrics. For this analysis, we have proposed a DMGC CGAA FET by amalgamating the gate and channel engineering techniques and the temperature is varied from 250K to 450K. A significant improvement in Ion/Ioff, SS, and DIBL by an amount of 96.98%, 19.49%, and 51.26% is obtained respectively for the proposed DMGC CGAA FET as compared to the single material graded channel (SMGC) CGAA FET. As the temperature is reduced from 450K to 250K, a noticeable improvement in analog/RF figure of merits and delay is obtained. Further, the self-heating effect (SHE) analysis revealed that the utilization of lower Rth is preferrable to minimize SHE in the device. Moreover, linearity parameters like gm2, gm3, VIP2, VIP3, IIP3 and IMD3 are noticed to be better for lower temperatures at higher VGS indicating good linearity. The obtained results make proposed device an ideal choice for various applications especially that operate in low temperature environments such as deep space, military, and RF applications.

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“…Adding sufficient underlap in the FinFET structure can limit S/D junction creation to the underlap portion and increase SCE susceptibility. 13,14 The analog performance of the device is mainly influenced by the gate electrostatics and reducing the oxide thickness, formation of thin and tall fins, and controlling the doping profiles are vital aspects of performance enhancements at nano-scale regions. 15,16 Nevertheless, in a fabrication point of view, creating such thin and tall fins for enhanced drive currents and improved SCEs presents several difficulties.…”

mentioning

confidence: 99%

Design Considerations into Circuit Applications for Structurally Optimised FinFET

Sarangam,

Valasa,

Mudidhe

et al. 2023

ECS J. Solid State Sci. Technol.

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FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (Lg), fin width (Wfin) and fin height (Hfin) for the duak-k spacer FinFET is performed and it is found that lowering the Lg and Wfin, and increasing the Hfin would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.

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Performance Analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap

Cited by 5 publications

References 19 publications

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

Design Considerations into Circuit Applications for Structurally Optimised FinFET

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