An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Abstract

The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

“…Moreover, the reduction in L g diminishes the overall resistance with in the channel, impeding the flow of charge carriers, a greater number can move from the source to the drain under the same V GS , leads to an overall increase in I on . 29 However, the increase in channel length reduces the leakage current (I off ), due to reduction of SCEs further leads to increase in overall switching ratio (I on /I off ) as depicted in Fig. 2d.…”