Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

Mudidhe, Praveen Kumar; Nistala, Bheema Rao

doi:10.1149/2162-8777/acec9e

Cited by 5 publications

(3 citation statements)

References 42 publications

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“…Various physics models that includes Drift-diffusion, Hydrodynamic model 22,23 Fermi-Dirac statistics, MLDA model (quantum confinement effects), 21 SRH recombination, 24 Band-toband model, 25,26 auger model, Philips unified and Lombardi mobility models, 27 slotboom bandgap narrowing model are included in simulation setup for analysis purpose.…”

Section: T E O T T 1 High K Sio High Kmentioning

confidence: 99%

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Ramakrishna,

Valasa,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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FinFET is considered a potential contender in the era of Multigate field-effect transistors (FETs). Here, we present structural variations for Junctionless FinFET devices at the IRDS sub-5nm technology node. Four JL-FinFET novel structures are proposed, JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET. The electrical and analog/RF performance of these structures are compared and it is found that JL-DG-Inv-U-FinFET gives better performance in terms of minimizing short channel effects as well as in terms of analog/radio frequency characteristics. The ION/IOFF ratio values for (JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET) are observed as 8.5×106, 1.2×109, 2.04×108, and 1.1×1010, respectively. Similarly, the SS values are noted as 93.44, 70.87, 70.61, and 62.1 mV/dec for the respective configurations. The effect of variation in geometrical parameters such as gate length, U-shaped fin width, and U-shaped fin height on DC and analog/RF characteristics is also explored. It has been observed that the DC parameters such as Ion/Ioff ratio, SS are better for higher Lg, lower WU-fin, and higher HU-fin. Moreover, the JL-DG-Inv-U-FinFET-based common source amplifier produced a gain of 5.2. The results reported will aid device engineers in selecting better geometrical parameters to achieve improved JL-DG-Inv-U-FinFET performance.

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Section: T E O T T 1 High K Sio High Kmentioning

confidence: 99%

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Ramakrishna,

Valasa,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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“…Furthermore, graded channel (GC) concept is a type of channel engineering technique used to enhance the device performance wherein the source and drain ends are doped with higher and lower doping concentrations respectively. The scattering effects that hinder carrier transport can be reduced with help of GC doping resulting in enhanced carrier mobility [22,23]. This improvement in carrier mobility contributes to faster switching speeds, lower power consumption, and overall enhanced device performance.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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“…The gate surrounding the channel in NW-FETs enhances gate control, optimizing performance. [10][11][12] However, NW-FETs face challenges such as reduced drive currents, increased parasitic effects, and fabrication complexities. NS-FETs with a GAA structure offers several compelling advantages over FinFETs and NW-FETs, including higher current drivability, reduced short-channel effects, enhanced injection velocities, improved volume inversion, and extensive experimental and theoretical validation.…”

mentioning

confidence: 99%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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This comprehensive study delves into the intricate analysis of the electrical and analog/RF performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization process, various DC and analog/RF metrics were taken into account. It is observed that, as the gate length decreases (12 nm to 8 nm), there is an increment in drain induced barrier lowering (DIBL), switching ratio (Ion/Ioff), and subthreshold swing (SS). Conversely, reducing the size of TNS (and WNS) from 10 nm to 5 nm (and 20 nm to 10 nm, respectively) lead to notable improvements, with a 34.4% (21.01%) decrease in SS, 93.19% (58.86%) decrease in DIBL, and 98.6% (41.06%) increase in Ion/Ioff. Furthermore, the analog/RF performance metrics of the device is carefully examined across dimensional variations, revealing significant improvements at the optimal values. Additionally, the study extends to the evaluation of inverter circuit characteristics with DM JL Tree-FET. Remarkably, the static noise margin (SNM) and delay exhibit 337.3 mV and 3.053 ps, respectively, positioning the device as a prime candidate for applications demanding low power consumption and high-frequency operation in future technology nodes.

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Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

Cited by 5 publications

References 42 publications

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

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