Design Considerations into Circuit Applications for Structurally Optimised FinFET

Sarangam, K.; Valasa, Sresta; Mudidhe, Praveen Kumar; Narendar, Vadthiya; Kotha, Venkata Ramakrishna; Bhukya, Sunitha; Bheemudu, V.; Pothalaiah, S.

doi:10.1149/2162-8777/ad1619

Cited by 2 publications

(2 citation statements)

References 29 publications

(30 reference statements)

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“…Using dual-K spacers in the underlap region of FinFETs with tall and thin fins improve the analog performance of the device. A single stage CS amplifier simulated with the said device exhibited a gain of 1.8155 and proper 180°phase shift in the output [28]. A comprehensive study of TMD FinFETs presented in [29] states 25% improvement in I ON due to use of MoS 2 layer in Si fin.…”

Section: Finfetsmentioning

confidence: 96%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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Section: Finfetsmentioning

confidence: 96%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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“…As pitch sizes decrease, the need for enhanced fin structures with increased compactness, height, and slender design arises, posing concerns for both performance and manufacturing processes. [7][8][9] On the other hand, gate-all-around nanowire transistors (GAA NW-FETs) are expected to enhance device scaling due to their exceptional ability to control short channels and achieve high current density. GAA NW-FETs have emerged as a promising option for sub-7 nm technology nodes due to their superior electrostatic integrity compared to FinFETs and TFETs.…”

mentioning

confidence: 99%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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This comprehensive study delves into the intricate analysis of the electrical and analog/RF performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization process, various DC and analog/RF metrics were taken into account. It is observed that, as the gate length decreases (12 nm to 8 nm), there is an increment in drain induced barrier lowering (DIBL), switching ratio (Ion/Ioff), and subthreshold swing (SS). Conversely, reducing the size of TNS (and WNS) from 10 nm to 5 nm (and 20 nm to 10 nm, respectively) lead to notable improvements, with a 34.4% (21.01%) decrease in SS, 93.19% (58.86%) decrease in DIBL, and 98.6% (41.06%) increase in Ion/Ioff. Furthermore, the analog/RF performance metrics of the device is carefully examined across dimensional variations, revealing significant improvements at the optimal values. Additionally, the study extends to the evaluation of inverter circuit characteristics with DM JL Tree-FET. Remarkably, the static noise margin (SNM) and delay exhibit 337.3 mV and 3.053 ps, respectively, positioning the device as a prime candidate for applications demanding low power consumption and high-frequency operation in future technology nodes.

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Design Considerations into Circuit Applications for Structurally Optimised FinFET

Cited by 2 publications

References 29 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

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