Optimization of series resistance in sub-0.2 μm SOI MOSFETs

Ultrathin Ni silicides were formed on silicon-oninsulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi 2 layers were grown at temperatures > 450 • C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi 2 is about one order of magnitude lower than that of a NiSi layer on both As-and B-doped SOI and SSOI.

Section: Introductionmentioning

confidence: 98%

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

Knöll

Zhao

Habicht

et al. 2010

“…However, aggressively scaled silicon body thickness for UTB MOSFETs may lead to full consumption of the Si source/drain (S/D) region during the silicidation process [4], [5]. Without proper Schottky barrier height engineering at the silicide-silicon interface, silicide contact resistance R CSD would contribute to high external series resistance R EXT and would severely degrade the drive current performance [3], [6]. A low Schottky barrier height at the silicide contact and a low R CSD are needed, and should preferably be achieved with a simple integration scheme.…”

Section: Introductionmentioning

confidence: 99%

Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain

Wong

Chan²,

Samudra

et al. 2009

We report the first integration of selenium (Se) segregation contact technology in ultrathin-body (UTB) n-MOSFET featuring Ni fully silicided source and drain. During the Ni silicidation process, the implanted Se segregated at the NiSi-n-Si interface, leading to significant reduction of Schottky barrier height and contact resistance. The UTB n-MOSFETs integrated with Se segregation (SeS) contact technology show significant external series resistance reduction and drive current performance enhancement. Drain-induced barrier lowering and gate leakage current density are not adversely affected by the SeS process.Index Terms-Schottky barrier, selenium segregation, silicide contact resistance, ultrathin body (UTB).

“…The function can be calculated by integrating the inversion charge along the channel [6] or by comparing (1) with the drain current expression given in [3]. The following equation is obtained if we follow the latter method: (2) where is the front gate-source voltage, is the threshold voltage (calculated as reported in [3]), and the front and back oxide capacitance, the depletion capacitance, the silicon film thickness, the charge coupling parameter between 0741-3106/00$10.00 © 2000 IEEE the front and back gates (it depends on the operating region of the back surface [8]) and (3) is a parameter to account for the drain-induced conductivity enhancement (DICE) [3]. This effect does not allow us to use the gradual channel approximation due to the important influence of the drain potential on the current, therefore a two-dimensional (2-D) potential and charge description of the device is necessary and is accomplished using this model.…”

Section: Drain Current Modelmentioning

confidence: 99%

“…The reduction of short channel effects in deep submicrometer SOI MOSFET's has encouraged the trend toward ultrathin silicon films [2]. However, the most important drawback linked to silicon film reduction is the increase of the series resistance, mostly in fully-depleted devices.…”

Section: Introduction S Ilicon-on-insulator (Soi) Technology Has Beenmentioning

confidence: 99%

Deep submicrometer SOI MOSFET drain current model including series resistance, self-heating and velocity overshoot effects

Roldán

Gamiz

López‐Villanueva³

et al. 2000