No abstract

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component εxx and the vertical strain component εzz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-oxide-semiconductor transistors.

The device physics and electrical characteristics of the germanium (Ge) tunneling field-effect transistor (TFET) are investigated for high performance and low power logic applications using two dimensional device simulation. Due to the high band-to-band tunneling rate of Ge as compared to Si, the Ge TFET suffers from excessive off-state leakage current Ioff despite its higher on-state current Ion. It is shown for the first time that the high off-state leakage due to the drain-side tunneling in the Ge TFET can be effectively suppressed by controlling the drain doping concentration. A lower drain doping concentration reduces the electric field and increases the tunneling barrier width in the drain side, giving a significantly reduced off-state leakage. To increase Ion with a steeper subthreshold swing S, source doping concentration is increased to reduce the bandgap and narrow the tunneling width. Device design and physics detailing the impact of drain and source engineering on the performance of Ge TFET are discussed.

The device physics of the double-gate tunneling field-effect transistor (DG TFET) is explored through two dimensional device simulations. The on-state drain current Ion of the DG TFET, which is based on band-to-band tunneling, has a strong dependence on the silicon film thickness TSi and the physics governing it is detailed. It is established that band-to-band tunneling at the surface is very strong and accounts for a large part of the total drain current. However, a substantial part of the total drain current Ids is contributed by a subsurface portion of the silicon film. Detailed potential distributions show that the coupling of two gate electrodes in the DG TFET could effectively reduce the tunneling width ωT at the center of the silicon film up to an optimum TSi where maximum drain current is obtained.

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