Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications

Abstract

The device physics and electrical characteristics of the germanium (Ge) tunneling field-effect transistor (TFET) are investigated for high performance and low power logic applications using two dimensional device simulation. Due to the high band-to-band tunneling rate of Ge as compared to Si, the Ge TFET suffers from excessive off-state leakage current Ioff despite its higher on-state current Ion. It is shown for the first time that the high off-state leakage due to the drain-side tunneling in the Ge TFET can be effectively suppressed by controlling the drain doping concentration. A lower drain doping concentration reduces the electric field and increases the tunneling barrier width in the drain side, giving a significantly reduced off-state leakage. To increase Ion with a steeper subthreshold swing S, source doping concentration is increased to reduce the bandgap and narrow the tunneling width. Device design and physics detailing the impact of drain and source engineering on the performance of Ge TFET are discussed.

Design Optimization of Extremely Short-Channel Graded Si/Sige Heterojunction Tunnel Field-Effect Transistors for Low Power Applications

“…Parameters A and B depend on the carrier effective mass m e , the smaller m e is, the higher is the BTBT current. The effect of small m e in Si 1-x Ge x on the tunneling current is taken into account by modifying parameters A and B to be 2.24×10 21 (eV) 1/2 /cmsV 2 and 15.7×10 6 V/cm(eV) 3/2 , respectively [20]. Eq.…”

“…The first method relates to modifying the structure of TFETs, such as double-gate [15], asymmetric structures [4], [16], ultra-thin body [11], gate-source/drain overlap/underlap [17,18], and heteromaterial gate [19]. Alternative method concentrates on changing the material properties, such as low bandgap materials [4,8], high-k gate dielectrics [15], and source/drain doping engineering [16,20]. Among these techniques, an asymmetric structure of heterojunction is the most effective technique that is extremely helpful in overcoming the conflict between on-and off-currents to simultaneously achieve high on-current and low off-leakage [16].…”

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

“…On the other hand, it has been pointed out that silicon-based TFETs have rather low on-state current (I on ), which makes it less competitive in high performance (HP) applications. This weakness can be mostly overcome by switching silicon to narrower bandgap material for higher tunneling efficiency at the source side and the channel material to semiconductor of high electron mobility [4][5][6]. In order to integrate these materials with silicon CMOS circuits, lattice mismatches should be resolved above all.…”

Ge p-channel tunneling FETs with steep phosphorus profile source junctions

“…The high source impurity concentration and steep source impurity profile can decrease the tunneling distance at source junctions, leading to the enhancement of the ON current. 16,17) However, it is difficult to realize such source junctions in Ge p-channel TFETs (p-TFET) because of the low solid solubility limit and high diffusivity of n-type dopants in Ge. [19][20][21] Defect-free source junctions are also needed to suppress trap-assisted tunneling and generation-recombination processes, which increase the leakage current.…”

“…The formation of source junctions with high impurity concentrations, 16) steep impurity profiles, 17) and low densities of defects 18) is the key to improving the TFET performance. The high source impurity concentration and steep source impurity profile can decrease the tunneling distance at source junctions, leading to the enhancement of the ON current.…”