Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction

Abstract

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Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

“…The tunnel FET has been given much attention in this regard as an alternative device architecture exhibiting a subthreshold swing (SS) below the conventional limits of MOSFET i.e. 60mV/dec, a low leakage current, suppressed Short Channel Effects (SCE) [1,2] and CMOS compatible process flow [3]. Numerous device designs and optimization techniques (both experimental and simulation based) such as strain engineering, heterojunction architectures, usage of low bandgap materials, tunnel source MOSFET [4][5][6][7][8][9], have been proposed in recent years in order to improve upon the shortcomings of TFET (a low ON current being the major bottleneck).…”

Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

“…With the BTBT mechanism, TFET suggests a breakthrough of SS < 60 mV/decade at 300 K. Despite the steep switching feature, the TFET performance (e.g., I ON $ 1:7 µA/µm at V DD of 1 V [9]) is not sufficient even for low-power applications. To improve the performance, hetero-junction TFETs with narrow band-gap materials (such as Ge or III-V materials) in the source region are proposed [5,6,7]. However, another disadvantage of TFETs still remained unsolved: the asymmetry of the TFET device structure requires more area in the layout when the devices are connected.…”

“…Because reducing V DD has become a critical issue for manageable power density, the tunnel field effect transistor (TFET) is proposed, providing scaling of V DD down to 0.5 V or even below due to the subthreshold slope (SS) less than 60 mV/decade. However, the various types of TFETs suggested so far [1,2,3,4,5,6,7] are not symmetric, resulting in an area penalty in layout. In a previous work [8], a novel symmetric tunnel field-effect transistor (S-TFET) was proposed as an alternative device structure for low-power applications.…”

(Thomas D. Callinan Award of the Dielectric Science and Technology Division) Ge-Source TFETs for Ultra-Low-Power Electronics

“…A heterojunction design, in which Ge is used only in the source region, is necessary to maintain low off-state leakage current (I OFF ) (5,6). The structure illustrated in Figure 1 was fabricated using a moderately doped poly-Ge source refill process to achieve the highest TFET I ON /I OFF reported to date for low-voltage (0.5 V) operation (7).…”