New method for the extraction of MOSFET parameters

a b s t r a c tIn this work double-gate pentacene TFT architecture is proposed and experimentally investigated. The devices are fabricated on a polyimide substrate based on a process that combines three levels of stencil lithography with standard photolithography. Similarly to the operation of a conventional double-gate silicon FET, the top-gate bias modulates the threshold voltage of the bottom-gate transistor and significantly improves the transistor sub-threshold swing and leakage current. Moreover, the double gate TFT shows good promise for the enhancement of I ON /I OFF , especially by the control of I OFF in devices with poor top interfaces.

Section: Low Field Carrier Mobility Lmentioning

confidence: 99%

Double-gate pentacene thin-film transistor with improved control in sub-threshold region

Tsamados

Cvetkovic

Sidler

et al. 2010

“…Since the bulk current does not change above V FB and not contributing significantly in the conduction in that regime, low-field electron mobility in the accumulation regime can be extracted simply using the I D = ffiffiffiffiffiffi g m p method [15] in the strong accumulation regime, independent of series resistance and mobility attenuation factor. To extract the low-field electron mobility, a cylindrical model, similar to [16], was used to expect the C ox value for the GAA deeply scaled nanowires.…”

Section: Low-field Electron Mobility Extraction In Accumulation Regimementioning

confidence: 99%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

a b s t r a c tIn this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve P2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm 2 /V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to %400 K and a V TH drift of À1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.

“…We also evaluated using carrier mobility of pFETs (a), (d), and (e) using Y-function method [30,31] and the low-field mobility µ 0 of 65.7, 43.9, and 68.1 cm 2 /Vs, respectively, was obtained.…”

Section: Tables 1 and 2)mentioning

confidence: 99%

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Sato

Kakushima

Ahmet

et al. 2011

Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. <100>-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (100)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100 o at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded.Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100 o is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs.