Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Abstract

a b s t r a c tIn this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve P2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm 2 /V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to %400 K and a V TH drift of À1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.

Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

“…Figure 2(a) and 2(b) shows the calibration of our TCAD simulation data with published experimental and analytical/theoretical work of M. Najmzadeh et al and J. Xiao‐shi et al respectively. Figure 2a shows the variation of drain current with gate voltage V gs , and Fig.…”

High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments

“…However, another concern comes from the lack of a feasible method for forming such suspended silicon nanowire with an accurately controlled size and cross-sectional shape, which is quite critical to the device variability suppression and mobility behavior. The existing works did not achieve either process variation suppression [10] or a precisely-controlled equilateral triangle [7,11], and also did not give the mobility characterization at a low temperature, which reflects the surface roughness scattering [12].…”

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

“…3 shows the second derivative of the total electron density per unit length (d 2 N t /dV 2 GS ) versus V GS for the GAA 15 nm wide Si NW MOSFETs for three channel doping concentrations, considering classical and quantum effects. The results reported in Table I show that the quantization is upshifting both the threshold and the flat-band voltages, due to the higher quantized subband energies [9], [23], [24]. Note that, even for the heavily doped structure and on the contrary to the IM devices [19], there is no hump effect below the gate voltage corresponding to the main peak in the d 2 N t /dV 2 GS versus V GS curve, thus representing a unique threshold voltage in the system.…”

“…Najmzadeh issues for ultra short channel devices. The multi-gate architectures (except circular cross-sections that can be obtained by hydrogen annealing [3] or stress-limited oxidation [4]) have corners (e.g., see [5]- [9]). Therefore, an in-depth analysis of the corner effect on the electrical characteristics of the multigate devices is necessary.…”