Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

Trivedi, Nitin; Kumar, Manoj; Haldar, Subhasis; Deswal, S. S.; Gupta, Mridula; Gupta, Rashmi

doi:10.1002/jnm.2162

Cited by 33 publications

(9 citation statements)

References 19 publications

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“…To resolve the issue of ON-current reduction, Junction Accumulation Mode (JAM) FET has been introduced [5]- [6]. The scheme of maintaining heavy doping in the source/drain region, while lowering the channel doping, enhances both the I ON , and I ON : I OF F ratio compared to those in JLFET [7]- [8]. At the ON-state, high electric field at the channel/drain interface gives rise to the hot-electron effects (HCEs) and gate induced drain leakage (GIDL).…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

Goswami

Chattopadhyay²,

Bose

2021

Preprint

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The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. The device is also simulated using Silvaco device simulator. Both the analytical and simulation results are compared and found to match closely. Quasi 3-D modeling approach is adopted here to determine the surface potential of the above device. In this technique, the entire 3-D device is segregated into two 2-D devices with certain physical constraints. These 2-D devices are then analyzed separately to obtain the surface potentials, which are added together using suitable multiplication factors to get the surface potential of the 3-D device. This surface potential is, in turn, used to model the threshold voltage, sub-threshold drain current ( I d,sub ) and the drain induced barrier lowering (DIBL). The proposed device configuration reduces the I OFF significantly and offers excellent immunity to SCEs. The response of the proposed device is studied for the variations of certain device parameters, such as, thickness of High- K dielectric layer in stack gate, channel doping, and the workfunctions as well as lengths of the gate metals. Such study will lead to turn the proposed device immune to short channel effects through proper choice of various parameters.

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Section: Introductionmentioning

confidence: 99%

Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

Goswami

Chattopadhyay²,

Bose

2021

Preprint

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

Goswami

Chattopadhyay²,

Bose

2021

Silicon

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“…Hu et al analyzed the subthreshold characteristics [17] and Trivedi et al proposed a current-voltage characteristic model of a junctionless cylindrical structure [18]. However, their analyses were only for channel lengths of 10 nm or more.…”

Section: Introductionmentioning

confidence: 99%

SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET

Jung¹

2020

IJECE

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We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/Lg)10-7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.

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Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

Cited by 33 publications

References 19 publications

Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET

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