Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

Abstract

Abstract-In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 19 , 5 × 10 18 , and 1 × 10 18 cm −3 were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO 2 gate oxide thickness (V DS = 0 V; T = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, N acc t /(CW eff ), in strong accumulation regime.

Estimation of doping in junctionless transistors through dc characteristics

“…This is due to the combination of vertical (side) and lateral (top) gates as well as corners which influences the potential distribution and gate capacitance. It has been reported that corners impact the device performance, and in particular, the capacitance above flatband [42][43][44][45][46] as the peak value of gate capacitance (in deep surface accumulation, V gs ?V fb ) has nonzero and finite contribution of corners. In a triple gate JL MOSFET with various Aspect Ratios (AR=H fin /T fin ) i.e.…”

“…The value of f in equation ( 14) is not fixed rather V gs dependent and shows significant contribution to total gate capacitance after flatband voltage. For V gs ?V fb , the majority of carriers accumulate at the corners as compared to the surface of the device [45,46] Finally, γ for TG JL transistor can be understood through the ratio of C gg(T) at V gm_avg to the maximum value of C gg(T) in the deep accumulation i.e. The gate capacitance estimated from the simplified expression (equation ( 16)) has been compared with the simulated capacitance values, and the expression provides a decent agreement for V gs >V fb for three different AR values with L g =200 nm,…”

Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

“…In JAM‐CSG, at source–channel–drain boundaries, the carriers are accumulated similar to an ohmic contact. To understand the subthreshold behavior of the device off‐current of the device must be investigated .…”

Characteristics of cylindrical surrounding-gate GaAs x Sb 1− x /In y Ga 1− y

“…Previous work focused on the planar GaAs x Sb 1−x /In y Ga 1−y As heterojunction TFETs. [13,14] Research on the performance of the SG mixed-As/Sb heterojunction TFET with cylindrical cross-section, which can eliminate the corner effect, [15] has not been found so far in the literature.…”